maxq7670aatl+ Maxim Integrated Products, Inc., maxq7670aatl+ Datasheet - Page 22

• Manufacturer Part Number: maxq7670aatl+
• Description: Microcontroller With 12-bit Adc, Pga, 64kb Flash, And Can Interface
• Manufacturer: Maxim Integrated Products, Inc.

Microcontroller with 12-Bit ADC,
PGA, 64KB Flash, and CAN Interface
The MAXQ7670A oscillator module provides the master
clock generator that supplies the system clock for the
µC core and all of the peripheral modules. The high-fre-
quency oscillator operates with an 8MHz or 16MHz
crystal. Alternatively, use the integrated RC oscillator in
applications that do not require precise timing. The
MAXQ7670A executes most instructions in a single
SYSCLK period. The oscillator module contains all of
the primary clock generation circuitry. Figure 7 shows a
block diagram of the system clock module.
The MAXQ7670A contains the following features for
generating its master clock signal timing source:
• Internal, fast-starting, 15MHz RC oscillator eliminates
• Internal high-frequency oscillator that can drive an
• External high-frequency 0.166MHz to 16MHz clock input
• Power-up timer
• Power-saving management modes
• Fail-safe modes
The primary function of the watchdog timer is to super-
vise software execution, watching for stalled or stuck
software. The watchdog timer performs a controlled
system restart when the µC fails to write to the watch-
dog timer register before a selectable timeout interval
expires. A watchdog timer typically has four objectives:
1) To detect if a system is operating normally
Figure 7. High-Frequency and RC Oscillator Functional
Diagram
22
external crystal
external 8MHz or 16MHz crystal
XOUT
XIN
RCE
______________________________________________________________________________________
XT
XTAL
OSC
OSC
HFE
RC
HF
EXTHF
System Clock Generator
CLK_RC
MUX
CD1
Watchdog Timer
CLOCK
DIVIDE
CD0 PMME
SYSCLK
2) To detect an infinite loop in any of the tasks
3) To detect an arbitration deadlock involving two or
4) To detect if some lower priority tasks are not getting
As illustrated in Figure 8, the internal RC oscillator
(CLK_RC) drives the watchdog timer through a series
of dividers. The programmable divider output deter-
mines the timeout interval. When enabled, the interrupt
flag WDIF sets. A system reset occurs after a time
delay (based on the divider ratio) unless an interrupt
service routine clears the watchdog interrupt.
The watchdog timer functions as the source of both the
watchdog interrupt and the watchdog reset. The inter-
rupt timeout has a default divide ratio of 2
CLK_RC, with the watchdog reset set to timeout 2
clock cycles later. With the nominal RC oscillator value
of 15MHz, an interrupt timeout occurs every 0.273ms,
followed by a watchdog reset 34µs later. The watchdog
timer resets to the default divide ratio following any
reset event. Use the WD0 and WD1 bits in the WDCN
register to increase the watchdog interrupt period.
Changing the WD[1:0] bits before a watchdog interrupt
timeout occurs (i.e. before the watchdog reset counter
begins) resets the watchdog timer count. The watch-
dog reset timeout occurs 512 RC oscillator cycles after
the watchdog interrupt timeout. For more information on
the MAXQ7670A watchdog timer, refer to the
MAXQ7670 User’s Guide.
Figure 8. Watchdog Functional Diagram
CLK_RC
(15MHz)
more tasks
to run because of higher priority tasks
WD1
WD0
RWT
DIV 2
12
2
12
2
15
TIME
DIV 2
2
TIMEOUT
18
RESET
WDIF
3
2
21
EWDI
EWT
DIV 2
3
DIV 2
12
3
INTERRUPT
WTRF
RESET
of the
9