maxq7666batm Maxim Integrated Products, Inc., maxq7666batm Datasheet - Page 42

• Manufacturer Part Number: maxq7666batm
• Description: 16-bit, Risc, Microcontroller-based, Smart Data-acquisition System
• Manufacturer: Maxim Integrated Products, Inc.

16-Bit, RISC, Microcontroller-Based,
Smart Data-Acquisition System
Table 3. System Register Bit Functions and Reset Values
* Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the
MAXQ7665/MAXQ7666 User’s Guide for more information.
42
PFX[n] (0..15)
REGISTER
A[n] (0..15)
WDCN
CKCN
GRXL
DP[0]
DP[1]
LC[0]
LC[1]
OFFS
APC
DPC
GRL
GRS
GRH
PSF
IMR
_______________________________________________________________________________________
GR
AP
SC
BP
IIR
SP
FP
IC
IP
IV
GR.15
GR.7
GR.7
15
—
—
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
GR.14
GR.6
GR.7
14
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.13
GR.5
GR.7
13
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.12
GR.4
GR.7
12
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.11
GR.3
GR.7
11
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.10
GR.2
GR.7
10
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.9
GR.1
GR.7
—
—
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.8
GR.0
GR.7
—
—
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REGISTER BIT
PFX[n] (16 Bits)
DP[0] (16 Bits)
DP[1] (16 Bits)
LC[0] (16 Bits)
LC[1] (16 Bits)
A[n] (16 Bits)
BP (16 Bits)
FP (16 Bits)
IP (16 Bits)
IV (16 Bits)
GR.15
GR.15
GR.7
GR.7
GR.7
CLR
POR
IMS
TAP
IIS
XT
—
—
—
—
s*
s*
Z
7
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR.14
GR.14
EWDI
GR.6
GR.6
GR.6
IDS
—
—
—
—
—
—
s*
—
—
S
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RGMD
CGDS
GR.13
GR.13
CDA1
GR.5
GR.5
GR.5
WD1
IM5
II5
—
—
—
—
—
s*
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CDA0
WBS2
GR.12
GR.12
GPF1
STOP
WD0
GR.4
GR.4
GR.4
IM4
—
—
—
II4
—
OFFS (8 Bits)
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
GR.11
GR.11
WBS1
GPF0
WDIF
GR.3
GR.3
GR.3
SWB
UPA
IM3
II3
—
—
3
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
MOD2
GR.10
GR.10
WTRF
WBS0
GR.2
GR.2
GR.2
ROD
IM2
OV
II2
—
—
s*
2
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
AP (4 Bits)
SP (4 Bits)
SDPS1
MOD1
GR.1
GR.1
GR.9
GR.9
GR.1
PWL
EWT
INS
IM1
II1
s*
—
s*
C
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDPS0
MOD0
GR.0
GR.0
GR.8
GR.8
GR.0
RWT
CD0
IGE
IM0
II0
—
0
0
0
E
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0