e-stlc3095 STMicroelectronics, e-stlc3095 Datasheet
e-stlc3095
Related parts for e-stlc3095
e-stlc3095 Summary of contents
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... DC/DC converter controller that drives an external MOS switch. February 2007 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Integrated POTS interface for home access gateway and WLL TQFP44 The battery level is properly adjusted depending on the operating mode ...
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... Applications diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Appendix A STLC3095 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Appendix B STLC3095 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Appendix C Typical state diagram for STLC3095 operation Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/28 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 High impedance feeding (HI- Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STLC3095 ...
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... GAIN SET 6 N.C. 7 DET 8 RES 9 RES RES 10 RES Block diagram and pin description DET OUTPUT LOGIC BGND TIP LINE OUTPUT DRIVER STAGE RING CREV DC PROC CSVR CLK RSENSE DC/DC GATE CONV. VF Vcc CVCC VPOS Vss VOLT. ...
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... Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally 23 CLK generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled. Driver for external Power MOS transistor (P-channel in Buck-boost configuration GATE channel in Fly-back configuration) ...
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... Off-hook threshold programming pin (via RTH). RTH should be connected close to this 31 RTH pin and AGND pin to avoid noise injection. DC feedback and ring trip input. RD should be connected close to this pin and AGND pin avoid noise injection. 33 ILTF Transversal line current image output ...
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... Pin D0, D1, D2, DET, PD dig T Ambient operating temperature range op (1) V Self generated battery voltage bat 1. Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see 6/28 Parameter Parameter Table 10 STLC3095 Value Unit -0 ...
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... External components as listed in the “Typical Values” column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25°C. Characterization as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85°C. Table 5. ...
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... RX gain variation vs. G24f freq. Idle channel noise at line V2Wp 0dB gainset Idle channel noise at line V2Wp 0dB gainset Idle channel noise at line V4Wp 0dB gainset Idle channel noise at line V4Wp 0dB gainset Total Harmonic Thd Distortion CLKfreq CLK operating range ...
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... Trtd Ring trip detection time Td Dialling distortion (1) Rlrt Loop resistance ThAl Tj for th. alarm activation DIgital Interface Inputs: D0, D1, D2, PD, CLK - Outputs: DET Vih In put high voltage Vil Input low voltage Iih Input high current Iil Input low current Vol Output low voltage Test Condition ACT. mode, RTH = 32.4kΩ ...
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... PSERRC Vpos to 2W port Vpos supply current Ivpos @ Peak current limiting (2) Ipk accuracy Maximum loop resistance (incl. telephone) for correct ring trip detection. lrt 2. Buck Boost configuration. 10/28 Test Condition Vripple = 100mVrms 50 to 4000Hz HI-Z On-Hook ACTIVE On-Hook, RING (line open) RING Off-Hook RSENSE = 130mΩ ...
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... DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements. The SLIC performs the standard feeding, signalling and transmitting functions. It can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low). ...
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... Power down When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance. Also the line detectors are disabled therefore the off-hook condition cannot be detected. This mode can be selected in emergency condition when it is necessary to cut any current delivered to the line ...
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... R resistor. SENSE AC characteristics The SLIC provides the standard SLIC transmission functions: Once in active mode the SLIC can operate with two different Tx, Rx gains respectively set by the gain set control bit (see Table 7. Gain set in active mode Gain set wire gain ...
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... ZAC impedance. ● Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output with a -6dB or -12dB gain and from the RX input to the 2W port with a 0dB or +6dB gain. ● wire conversion: The balance impedance can be real or complex, the proper ...
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... RSENSE. This also limits the power available at the self generated negative battery. If for any reason the ringer load is too low the self generated battery drops in order to keep the power consumption to the fixed limit. Consequently, the ring voltage level is also reduced ...
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... STLC3095 using small chokes, ● by adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch frequency on VPOS. 3.2.6 External components list In order to properly define the external components value the following system parameters have to be defined: ● ...
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... CVpos should be defined depending on the power supply current capability and maximum allowable ripple. 2. For low ripple application use 2x47 µF in parallel. 3. Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). 4. For high efficiency in HI-Z mode coil resistance @125kHz must be < 3 Ω . ...
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... RSENSE limiting DC/DC converter switch Q1 N-channel MOS transistor D1 DC/DC converter series diode T1 DC/DC Converter transformer 18/28 Formula RREF = 1.3/Ibias; Ibias = 50µA CSVR = 1/(2π ⋅ fp ⋅ 1.8MΩ 50Hz RD = 100/I RTH 2KΩ < RD < 5KΩ Rp > 30Ω RLIM = 1300/Ilim 52.3kΩ < RLIM < 65kΩ RTH = 290/I TH 27kΩ < RTH < 52kΩ ...
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... Line impedance balancing (5) ZB network CCOMP AC feedback loop compensation Trans-Hybrid Loss frequency CH compensation 1. In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|. Formula Fly-Back transformer 4W, Turns Ratio 1:8 fro VPOS range from 8.5V to 12V 250KΩ<RF1<270KΩ Formula ⋅ (2Rp) ZAC = 50 ⋅ ...
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... Applications diagram 4 Applications diagram Figure 7. Application diagram with N-channel DET CONTROL D0 INTERFACE SYSTEM GND SUGGESTED GROUND LAY-OUT Figure 8. Application diagram with P-channel DET CONTROL D0 INTERFACE SYSTEM GND SUGGESTED GROUND LAY-OUT 20/ RRX RX TX AGND BGND RS RS ZAC CCOMP ZAC1 ...
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... Appendix A STLC3095 test circuits Referring to the application diagram shown in the typical values specified in given below. All measurements requiring DC current termination should be performed using “Wandel & Goltermann DC Loop Holding Circuit GH-1” or equivalent. 2W Return loss - 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs) Figure 9. E Figure 10. THL Trans Hybrid Loss - THL = 20Log|Vrx/Vtx| ...
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... STLC3095 test circuits Figure 11. G24 Transmit Gain - G24 = 20Log|2Vtx/E| Figure 12. G42 Receive Gain - G42 = 20Log|VI/Vrx| Figure 13. PSRRC Power supply rejection Vpos to 2W port - PSSRC = 20Log|Vn/Vl| 22/28 W&G GH1 TIP 100µF 100mA DC max 600ohm Zin = 100K 200 to 6kHz E 100µF RING W& ...
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... STLC3095 Figure 14. T/L Transversal to Longitudinal Conversion - T/L = 20Log|Vrx/Vcm| 600ohm Figure 15. V2Wp and W4Wp: Idle channel psophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l| Vl psophometric filtered W&G GH1 100µF 300ohm 100µF 100mA DC max Impedance matching better than 0.1% Zin = 100K 200 to 6kHz Vcm 100µ ...
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... STLC3095 over voltage protection Appendix B STLC3095 over voltage protection Figure 16. Simplified configuration for indoor over voltage protection Figure 17. Standard over voltage protection configuration for K20 compliance 24/28 STPR120A BGND STLC3095 STLC3085N RP1 TIP RP1 RING VBAT STPR120A RP1 = 30ohm: RP2 =Fuse or PTC > 20ohm ...
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... STLC3095 Appendix C Typical state diagram for STLC3095 operation Figure 18. Typical state diagram for STLC3095 operation Tj>Tth PD=1, D0=D1=0 On Hook Condition Note: all state transitions are under the microprocessor control. Typical state diagram for STLC3095 operation PD=0, D0=D1=0 Power Down Ring Burst Ring Burst D0=1, D1=0, D2=0/1 On Hook Detection for T>Tref ...
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... Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK specifications are available at: www.st.com Figure 19. TQFP44 (10x10x1.4mm) mechanical data & package dimensions DIM ...
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... STLC3095 6 Ordering information Table 13. Order codes Part number (1) E-STLC3095 1. ECOPACK® (see 7 Revision history Table 14. Document revision history Date 08-Feb-2007 Temp range, ° (*) Section 5 ) Revision 1 Initial release. Ordering information Package Packing TQFP44 Tube Changes 27/28 ...
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