lm9820ccwmx National Semiconductor Corporation, lm9820ccwmx Datasheet - Page 8

• Manufacturer Part Number: lm9820ccwmx
• Description: 10/12-bit Image Sensor Processor Analog Front End
• Manufacturer: National Semiconductor Corporation

Pin Descriptions
V
V
VA
AGND
OS
RefBypass
MCLK
SampCLK
NewLine
REF+
REF-
R
,
,
OS
V
REFMID
G
,
OS
,
B
,
This is the positive supply pin for the analog
supply. It should be connected to a voltage
source of +5V and bypassed to
0.1µF monolithic capacitor in parallel with a
10µF tantalum capacitor.
This is the ground return for the analog sup-
ply.
Analog Inputs. These inputs (for Red,
Green, and Blue) should be tied to the sen-
sor’s OS (Output Signal) through DC block-
ing capacitors.
Internally generated reference voltage
bypass pin. It should be bypassed to
through a .05uF monolithic capacitor.
Voltage reference bypass pins. They should
each be bypassed to
monolithic capacitor.
Master Clock. The ADC conversion rate will
be a maximum of ¼ of
24MHz.
Sample Clock.
version rate of the ADC (up to ¼ of the
MCLK
level is sampled while
held on the rising edge of
CDS is enabled, the falling edge of
causes the CCD reference level to be held.
If CDS is not enabled,
on the falling edge of
on the programmed signal polarity.
is also used with
nal coupling capacitors.
New Line signal. Used to indicate the start
of active pixels on a new line, to allow
clamping of the AC coupling caps, and to
allow programming of the configuration reg-
ister. When
low, the OS inputs will be connected to
either
of
mux and the offset and gain settings will be
set to the appropriate values for the first
color of the next line set in the color mode
setting in the Sampler and Color Mode Reg-
ister. When
the pixel conversion data from the ADC.
When
STATE and
interface for programming the configuration
registers.
Input & Timing Control
MCLK
Analog Power
rate) and sample timing. The signal
V
NewLine
Analog I/O
REF+
after
D2
NewLine
NewLine
or
NewLine
,
V
is high, D[5-0] enter TRI-
SampCLK
D1
REF-
NewLine
and
. On the first rising edge
is high and
is low, D[5-0] transmit
AGND
SampCLK
goes low, the internal
SampCLK
V
MCLK
D0
REF+
controls the con-
to clamp the exter-
SampCLK
act as a serial
through a .05uF
. Nominally
or
, depending
V
AGND
SampCLK
is low and
REF-
SampCLK
SampCLK
. When
is held
AGND
with a
is
8
D5
D5
D4
D3
D2
D1
D0
LM9820
Output Mode
(
D5
D4
D3
D2
D1
D0
VD
DGND
LM9810
Output Mode
(
Input Mode
(
D5
D2
D1
D0
NewLine
NewLine
NewLine
-
-
D0
(SCLK)
(Latch)
(SDI)
D3
Low)
Low)
High)
This is the positive supply pin for the digital
supply. It should be connected to a voltage
source of +5V and bypassed to
0.1µF monolithic capacitor.
This is the ground return for the digital sup-
ply.
Data Input/Output pins. When
low, the 10 or 12 bit conversion results of
the ADC are multiplexed to
NewLine
STATE and
face for writing to the configuration regis-
ters.
MCLK0, MCLK1, MCLK2, MCLK3
b9,
b8,
b7,
b6,
b5,
b4,
MCLK0, MCLK1, MCLK2, MCLK3
b11,
b10,
b9,
b8,
b7,
b6,
Don’t Care
Serial Data Clock.
Latch and shift enable signal. When
D1
When
shifted into
the addressed configuration register. To
avoid erroneous writes to the configuration
registers,
when
Serial input data. Data is valid on
rising edge. Three address bits followed by
six data bits (MSB first) should be shifted
into
(Latch) is low, data is shifted into
D0
Digital Power
NewLine
D1
before
Digital I/O
is high, the output drivers enter TRI-
(Latch) goes high, the last nine bits
b9,
b8,
b7,
b6,
b5,
b4,
b11,
b10,
b9,
b8,
b7,
b6,
D1
D0
D2
(Latch) should be pulled low
(SDI) will be used to program
is high.
,
D1
D1
(Latch) goes high.
&
b3,
b2,
b1,
b0,
0,
0,
b5,
b4,
b3,
b2,
b1,
b0,
D0
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act as a serial inter-
D5
b3
b2
b1
b0
0
0
b5
b4
b3
b2
b1
b0
-
NewLine
D0
DGND
. When
D2
D0
(SCLK)
(SDI).
with a
is