lm9820ccwmx National Semiconductor Corporation, lm9820ccwmx Datasheet - Page 15

• Manufacturer Part Number: lm9820ccwmx
• Description: 10/12-bit Image Sensor Processor Analog Front End
• Manufacturer: National Semiconductor Corporation

Applications Information
1.0 Programming the LM9810/20
1.1 Writing to the Configuration Register
When
ing to the configuration registers.
(SCLK),
shift enable signal (Latch). When
shifted into
D2
should be shifted into
tions from low to high, the last 6 data bits will be stored into the
configuration register addressed by the previous 3 address bits
(as shown in Diagram 3).
3 cycles of the serial clock on
tion register.
1.2 CDS Mode
The LM9810/20 uses a high-performance CDS (Correlated Dou-
ble Sampling) circuit to remove many sources of noise and error
from the CCD signal. It also supports CIS image sensors with a
single sampling mode.
Figure 1 shows the output stage of a typical CCD and the result-
ing output waveform:
Capacitor C1 converts the electrons coming from the CCD’s shift
register to an analog voltage. The source follower output stage
(Q2) buffers this voltage before it leaves the CCD. Q1 resets the
voltage across capacitor C1 between pixels at intervals 2 and 5.
When Q1 is on, the output signal (OS) is at its most positive volt-
age. After Q1 turns off (period 3), the OS level represents the
residual voltage across C1 (V
charge injection from Q1, thermal noise from the ON resistance
of Q1, and other sources of error. When the shift register clock
(Ø1) makes a low to high transition (period 4), the electrons from
the next pixel flow into C1. The charge across C1 now contains
the voltage proportional to the number of electrons plus V
UAL
that voltage is subtracted from the OS at the end of period 4, the
V
RESIDUAL
(SCLK). Three register address bits followed by six data bits
, an error term. If OS is sampled at the end of period 3 and
RS (RESET)
SampCLK
NewLine
D0
term is canceled and the noise on the signal is
is the input data pin (SDI), and
D0
RS
OS
Ø1
is high,
(SDI), and must be valid on each rising edge of
(from shift register)
1
D2
D0(SDI),
e-
,
Figure 1: CDS
2
D1
D1
Q1
(Latch) must remain high for at least
&
3
D2
D0
MSB first. When
(SCLK) to write to the configura-
RESIDUAL
act as a serial interface for writ-
D1
D2
(Latch) is low, serial data is
V
C1
DD
is the input serial clock
4
). V
V
Q2
SS
D1
RESIDUAL
D1
is the latch and
5
(Latch) transi-
OS
includes
RESID-
15
reduced ([V
principal of Correlated Double Sampling.
If the LM9810/20 is programmed for correlated double sampling
(bit B5 of register 0 is cleared), then the falling edge of
should occur toward the end of period 3 and the rising edge of
SampCLK
CLK
held at the falling edge of
nal level (V
ing edge of
difference between the two samples, or V
1.3 CIS Mode
The LM9810/20 supports CIS (Contact Image Sensor) devices by
offering a sampling mode for capturing positive going signals, as
opposed to the CCD’s negative going signal. The output signal of
a CIS sensor (Figure 2) differs from a CCD signal in two primary
ways: its output increases with increasing signal strength, and it
does not usually have a reference level as an integral part of the
output waveform of every pixel.
When the LM9810/20 is in CIS mode (Register 0, B5=1), it uses
either
of the Sampling and Color Mode register) as the reference (or
black) voltage for each pixel. If the signal polarity is set to one,
then
signal will be held on the rising edge of
zero, then
the OS signal will be held on the rising edge of
ing edge of
at least 50ns after the falling edge of
1.4 Multiplexer/Channel Switching
The offset and gain settings automatically switch after each ADC
conversion according to the color mode setting in the Sampler
and Color Mode register (register 0). For example, if the color
mode (bits B2,B1 & B0) is set to 001, the offset and gain will alter-
nately switch between the R, G and B settings after each conver-
sion. The input multiplexer never changes during a line, but if the
color mode is set to Line Rate Color (000), the mux will automati-
cally switch after each new line.
The offset and gain settings will always start with the first channel
of the programmed mode after a falling edge on
is high, the Reference level (V
V
REF-
V
SampCLK
REF+
OS (CIS)
OS (CCD)
should occur towards the end of period 4. While
will be held on the falling edge of
SIGNAL
V
SIGNAL
SampCLK
REF+
SampCLK
or
V
REF-
will be held on the falling edge of
+ V
+V
. The output from the sampler is the potential
depending on the signal polarity setting (B4
RESIDUAL
RESIDUAL
should occur near the end of period 4, and
1
SampCLK
Figure 2: CIS
2
) is sampled and it is held at the ris-
]-V
3
RESIDUAL
. While
RESIDUAL
SampCLK
SIGNAL
SampCLK
SampCLK
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= V
4
) is sampled, and it is
SampCLK
.
SIGNAL
SampCLK
.
. If it is set to
is low, the sig-
SampCLK
5
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). This is the
and the OS
. The ris-
SampCLK
Samp-
. For
and