max5864 Maxim Integrated Products, Inc., max5864 Datasheet - Page 20

• Manufacturer Part Number: max5864
• Description: Max5864 Ultra-low-power, High-dynamic-performance, 22msps Analog Front End
• Manufacturer: Maxim Integrated Products, Inc.

Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
Figure 8. Balun-Transformer Coupled Differential to Single-
Ended Output Drive for DACs
Figure 9. Single-Ended Drive for ADCs
20
V
V
IN
IN
______________________________________________________________________________________
100Ω
100Ω
100Ω
100Ω
MAX5864
0.1µF
0.1µF
QD+
QD-
ID+
REFP
REFN
REFP
REFN
ID-
1kΩ
1kΩ
1kΩ
1kΩ
R
50Ω
R
50Ω
0.1µF
0.1µF
ISO
ISO
22pF
22pF
22pF
22pF
R
50Ω
C
50Ω
C
C
R
C
ISO
IN
ISO
IN
IN
IN
V
V
OUT
OUT
INA+
COM
INA-
INB+
INB-
MAX5864
Drive the MAX5864 ADCs with op amps when a balun
transformer is not available.
ADCs being driven by op amps for AC-coupled single-
ended, and DC-coupled differential applications.
Amplifiers such as the MAX4354/MAX4454 provide
high speed, high bandwidth, low noise, and low distor-
tion to maintain the input signal integrity.
also be used to interface with the DAC differential ana-
log outputs to provide gain or buffering. The DAC dif-
ferential analog outputs cannot be used in single-
ended mode because of the internally generated
1.4VDC common-mode level. Also, the DAC analog
outputs are designed to drive a differential input stage
with input impedance ≥70kΩ. If single-ended outputs
are desired, use an amplifier to provide differential to
single-ended conversion and select an amplifier with
proper input common-mode voltage range.
The MAX5864 can be used in diverse applications
operating FDD or TDD modes. The MAX5864 operates
in Xcvr mode for FDD applications such as WCDMA-
3GPP (FDD) and 4G technologies. Also, the MAX5864
can switch between Tx and Rx modes for TDD applica-
tions like TD-SCDMA, WCDMA-3GPP (TDD),
IEEE802.11a/b/g, and IEEE802.16.
In FDD mode, the ADC and DAC operate simultaneous-
ly. The ADC bus and DAC bus are dedicated and must
be connected in 18-bit parallel (8-bit ADC and 10-bit
DAC) to the digital baseband processor. Select Xcvr
mode through the 3-wire serial interface and use the
conversion clock to latch data. In FDD mode, the
MAX5864 uses 34mW power at f
is the total power of the ADC and DAC operating simul-
taneously.
In TDD mode, the ADC and DAC operate independent-
ly. The ADC and DAC bus are shared and can be con-
nected together, forming a single 10-bit parallel bus to
the digital baseband processor. Using the 3-wire serial
interface, select between Rx mode to enable the ADC
and Tx mode to enable the DAC. When operating in Rx
mode, the DAC does not transmit because the core is
disabled and in Tx mode, the ADC bus is tri-state. This
eliminates any unwanted spurious emissions and pre-
vents bus contention. In TDD mode, the MAX5864 uses
24.7mW power in Rx mode at f
the DAC uses 24mW in Tx mode.
Using Op-Amp Coupling
Figures 9 and 10
FDD and TDD Modes
CLK
CLK
= 15.36MHz, and
= 15.36MHz. This
Figure 10
show the
can