max5864 Maxim Integrated Products, Inc., max5864 Datasheet - Page 17

• Manufacturer Part Number: max5864
• Description: Max5864 Ultra-low-power, High-dynamic-performance, 22msps Analog Front End
• Manufacturer: Maxim Integrated Products, Inc.

Table 3. MAX5864 Operation Modes
X = Don’t care.
Shutdown mode offers the most dramatic power savings
by shutting down all the analog sections of the MAX5864
and placing the ADCs’ digital outputs in tri-state mode.
When the ADCs’ outputs transition from tri-state to on,
the last converted word is placed on the digital outputs.
The DACs’ digital bus inputs must be zero or OV
because the bus is not internally pulled up. The DACs’
previously stored data is lost when coming out of shut-
down mode. The wake-up time from shutdown mode is
dominated by the time required to charge the capacitors
at REFP, REFN, and COM. In internal reference mode
and buffered external reference mode, the wake-up time
is typically 40µs to enter Xcvr moed, 20µs to enter Rx
mode, and 40µs to enter Tx mode.
In idle mode, the reference and clock distribution circuits
are powered, but all other functions are off. The ADCs’
outputs are forced to tri-state. The DACs’ digital bus
inputs must be zero or OV
internally pulled up. The wake-up time from the idle mode
is 10µs required for the ADCs and DACs to be fully oper-
ational. When the ADCs’ outputs transition from tri-state to
on, the last converted word is placed on the digital out-
puts. In the idle mode, the supply current is lowered if the
clock input is set to zero or OV
time extends to 40µs.
QSPI is a trademark of Motorola, Inc.
FUNCTION
Shutdown
Standby
Xcvr
Idle
Rx
Tx
D evi ce shutd ow n. RE F i s off, AD C s ar e
off, and the AD C b us i s tr i - stated ; D AC s
ar e off and the D AC i np ut b us m ust b e
set to zer o or OV
REF and CLK are on, ADCs are off,
and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OV
REF is on, ADCs are on; DACs are off,
and the DAC input bus must be set to
zero or OV
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are on.
REF is on, ADCs and DACs are on.
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are off and the
DAC input bus must be set to zero or
OV
______________________________________________________________________________________
DD
Performance, 22Msps Analog Front End
.
DD
DESCRIPTION
DD
.
DD
, because the bus is not
D D
DD
; however, the wake-up
.
.
Ultra-Low-Power, High Dynamic-
DD
(MSB)
D7
X
X
X
X
X
X
In standby mode, only the ADCs’ reference is powered;
the rest of the device’s functions are off. The pipeline
ADCs are off and DA0 to DA7 are in tri-state mode. The
DACs’ digital bus inputs must be zero or OV
because the bus is not internally pulled up. The wake-
up time from standby mode to the Xcvr mode is domi-
nated by the 40µs required to activate the pipeline
ADCs and DACs. When the ADC outputs transition from
tri-state to active, the last converted word is placed on
the digital outputs.
The serial digital interface is a standard 3-wire connec-
tion compatible with SPI/QSPI™/MICROWIRE/DSP
interfaces. Set CS low to enable the serial data loading
at DIN. Following CS high-to-low transition, data is shift-
ed synchronously, MSB first, on the rising edge of the
serial clock (SCLK). After 8 bits are loaded into the seri-
al input register, data is transferred to the latch. CS
must transition high for a minimum of 80ns before the
next write sequence. The SCLK can idle either high or
low between transitions.
timing diagram of the 3-wire serial interface.
D6
X
X
X
X
X
X
D5
X
X
X
X
X
X
D4
X
X
X
X
X
X
Figure 5
D3
X
X
X
X
X
X
D2
0
0
0
0
1
1
shows the detailed
D1
0
0
1
1
0
0
D0
0
1
0
1
0
1
DD
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