pi90sd1636c Pericom Semiconductor Corporation, pi90sd1636c Datasheet - Page 9

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pi90sd1636c

Manufacturer Part Number
pi90sd1636c
Description
Serdes Gigabit Ethernet Transceiver
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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07-0253
Table 9. Receiver Timing Characteristics
Notes:
1.
2.
Symbol
b_sync
f_lock
t
t
t
t
T_rxlat
SETUP
HOLD
DUTY
A-B
This is the recovery for input phase jumps.
The receiver latency as shown in Figure 6, is defi ned as the time between receiving the fi rst serial bit of a parallel data word (defi ned as the
fi rst edge of the fi rst serial bit) and the clocking out of that parallel word (defi ned by the rising edge of the receive byte clock, either RBC1 or
RBC0).
TX<9:0>
[1]
TX_CLK
[2]
TX<9:0>
TX_CLK
Parameter
Bit Sync Time
Frequency Lock at Powerup
Data Setup Before Rising Edge of RX_CLK
Data Hold After Rising Edge of RX_CLK
RX_CLK Duty Cycle
RX_CLK Skew
Receiver Latency
DOUT ±
T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
DATA
t
SETUP
Figure 3. Transmitter Section Timing
Figure 4. Transmitter Latency
t
HOLD
DATA BYTE B
T
A
= 0°C to +70°C, V
DATA BYTE A
DATA
t_TXLAT
9
DATA
Min.
2.5
1.5
7.5
40
CC
= 3.15V to 3.45V
SERDES Gigabit Ethernet Transceiver
DATA
DATA BYTE B
Typ.
22.4
28.0
DATA BYTE C
DATA
Max.
2500
500
8.5
60
1.4V
1.4V
2.0V
PI90SD1636C
0.8V
PS8922A
Unit
bits
bits
μs
ns
%
ns
ns
11/08/07

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