pi90sd1636c Pericom Semiconductor Corporation, pi90sd1636c Datasheet - Page 4

• Manufacturer Part Number: pi90sd1636c
• Description: Serdes Gigabit Ethernet Transceiver
• Manufacturer: Pericom Semiconductor Corporation

07-0253
Table 2. Pin Description
Name
GND_ESD
VCC_ESD
TX<0>
TX<1>
TX<2>
TX<3>
TX<4>
TX<5>
TX<6>
TX<7>
TX<8>
TX<9>
GND_TXA
VCC_TXA
NC
EWRAP
VCC_TXD
GND_TXD
TX_CLK
VCC_RXD
GND_RXD
EN_CDET
SIG_DET
VCC_RX
GND_RX
RX_CLK<1>
RX_CLK<0>
Pin #
1, 14
5, 10
2
3
4
6
7
8
9
11
12
13
15
18
16, 17,27,
48, 49
19
20
21
22
23 28,
25
24
26
29
32
30
31
Type
P
TTL_IN
P
NC
TTL_IN
P
TTL_IN
P
TTL_IN
TTL_
OUT
P
TTL_
OUT
Description
Power and ground pairs for pad ESD structure.
0-bit parallel data input pins. This data should be 10b/8b encoded. The least
signifi cant bit is TX<0> and is transmitted fi rst.
Power and ground pair for TX PLL analog circuits.
No Connect
Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial data
are internally wrapped from the transmitter serial data output back to the receiver
data input. Also, when asserted, DOUT± are held static at logic 1. When deasserted,
DOUT± and .DIN± are active.
Power and ground pair for TX digital circuits.
Reference clock and transmit byte clock. This is a 125 MHz system clock supplied
by the host system. On the positive edge of the clock, the input data, TX<9:0>, are
latched into the register. This clock is multiplied by 10 internally, to generate the
transmit serial bit clock.
Power and ground pair for digital circuits in the receiver portion.
Comma Detect Enable. This pin is active HIGH. When asserted, the internal byte
alignment function is turned on, to allow the clock to synchronize with the comma
character (0011111XXX). When de-asserted, the function is disabled and will not align
the clock and data. In this mode COM_DET is set to LOW.
Signal Detect. This pin is active HIGH. It indicates the loss of input signal on the
high-speed serial inputs, DIN±. SIG_DET is set to LOW when differential inputs are
less than 50 mV.
Power and ground pair for the clock signal of the receiver portion.
Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals that are
recovered by the receiver section. The received bytes are alternately clocked by the
rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma
character when detected.
4
SERDES Gigabit Ethernet Transceiver
PI90SD1636C
PS8922A
11/08/07