lmk03002c National Semiconductor Corporation, lmk03002c Datasheet - Page 7

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lmk03002c

Manufacturer Part Number
lmk03002c
Description
Precision Clock Conditioner With Integrated Vco
Manufacturer
National Semiconductor Corporation
Datasheet

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Note 9: VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the phase noise typically
varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies by 1 to 2 dB,
assuming the device is not reprogrammed. Reprogramming R15 will run the frequency calibration routine for optimum phase noise.
Note 10: The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications apply to the clock
distribution section only and is in RMS form addition to the jitter from the VCO.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: Applies to GOE, LD, and SYNC*.
Note 13: Applies to CLKuWire, DATAuWire, and LEuWire.
Serial Data Timing Diagram
30020603
Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On
the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits.
After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state.
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