w83194br-619 Winbond Electronics Corp America, w83194br-619 Datasheet - Page 3

• Manufacturer Part Number: w83194br-619
• Description: Winbond Clock Generator For Intel P4 Springdale Series Chipset P4 Springdale Series Chipset
• Manufacturer: Winbond Electronics Corp America

Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 1
PRODUCT FEATURES .............................................................................................................. 1
PIN CONFIGURATION ............................................................................................................... 2
BLOCK DIAGRAM ...................................................................................................................... 3
PIN DESCRIPTION..................................................................................................................... 4
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7
I
5.1 Crystal I/O .....................................................................................................................................4
5.2 CPU, SRC, 3V66, PCI Clock Outputs..........................................................................................4
5.3 Fixed Frequency Outputs .............................................................................................................5
5.4 I2C Control Interface.....................................................................................................................5
5.5 Output Control Pins ......................................................................................................................6
5.6 Power an GND Pins .....................................................................................................................6
7.1 Register 0: Frequency Select Register (Default =18H)...............................................................8
7.2 Register 1: SRC/CPU Clock Register (1 = Enable, 0 = Disable) (Default =E3H) ......................8
7.3 Register 2: PCI Clock Register (1 = Enable, 0 = Disable) (Default =FFH) .................................9
7.4 Register 3: PCI, 3V66 Clock Register (1 = Enable, 0 = Disable) (Default =EFH) ......................9
7.5 Register 4: 24_48MHz, REF Control Register (1 = Enable, 0 = Disable) (Default =FCH) ........9
7.6 Table-1: Clock output mode selection........................................................................................10
7.7 Register 5: Watchdog Control Register (Default =C0H) ...........................................................10
7.8 Register 6: Watchdog Timer Register (Default =08H)...............................................................11
7.9 Register 7: M/N Program Register (Default =40H)....................................................................11
7.10 Register 8: M/N Program Register (Default =8AH) ...................................................................12
7.11 Register 9: M/N Program Register (Default =CEH)...................................................................12
7.12 Register 10: M/N Program Register (Default =13H)..................................................................12
7.13 Register 11: Spread Spectrum Programming Register (Default =1FH) ...................................13
7.14 Register 12: Divider Ratio Register (Default =C6H) ..................................................................13
7.15 Table-2 CPU, SRC, AGP divider ratio selection Table .............................................................13
7.16 Register 13: Control Register (Default =0FH)............................................................................14
7.17 Register 14: Control Register (Default =32H)............................................................................14
7.18 Register 15: Control Register (Default =3AH) ...........................................................................15
7.19 Register 16: Control Register (Default =24H)............................................................................15
7.20 Register 17: Slew Rate Control Register (Default =55H)..........................................................15
7.21 Register 18: Slew Rate Control (Default =55H).........................................................................16
2
C CONTROL AND STATUS REGISTERS............................................................................... 8
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
W83194BR-619/W83194BG-619
- II -