mpc961p Integrated Device Technology, mpc961p Datasheet - Page 6

• Manufacturer Part Number: mpc961p
• Description: Lvpecl-input Lvcmos-ouput 200-mhz Low Voltage Clock Zero Delay Buffer
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage Zero Delay Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC961P
Low Voltage Zero Delay Buffer
looking into the driver. The parallel combination of the 36 Ω
series resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
reflection coefficient, to 2.62 V. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Figure 6
At the load end the voltage will double, due to the near unity
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 6. Optimized Dual Line Termination
VL = VS (Z
Z
R
R
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
Figure 5. Single versus Dual Waveforms
O
S
O
should be used. In this case the series terminating
= 1.31 V
OUTPUT
MPC961
BUFFER
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
14 Ω
t
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
2
D
= 3.8956
OutA
In
O
4
/ (R
25 Ω = 25 Ω
S
R
R
S
S
+ R
6
= 22 Ω
= 22 Ω
TIME (ns)
O
t
D
+Z
= 3.9386
OutB
8
O
))
Z
Z
O
O
= 50 Ω
= 50 Ω
10
12
14
6
engineers who want to simulate their specific interconnect
schemes.
Using the MPC961P in Zero-Delay Applications
Designs using the MPC961P as LVCMOS PLL fanout buffer
with zero insertion delay will show significantly lower clock skew
than clock distributions developed from CMOS fanout buffers.
The external feedback option of the MPC961P clock driver
allows for its use as a zero delay buffer. By using the QFB
output as a feedback to the PLL the propagation delay through
the device is virtually eliminated. The PLL aligns the feedback
clock output edge with the clock input reference edge resulting
a near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This effective
delay consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
Calculation of Part-to-Part Skew
critical clock signal timing can be maintained across several
devices. If the reference clock inputs of two or more MPC961P
are connected together, the maximum overall timing uncertainty
from the common PCLK input to any output is:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from
SPICE level and IBIS output buffer models are available for
Nested clock trees are typical applications for the MPC961P.
The MPC961P zero delay buffer supports applications where
This maximum timing uncertainty consist of 4 components:
Due statistical nature of I/O jitter a rms value (1σ) is
Figure 7. MPC961P Max. Device-to-Device Skew
TCLK
Any Q
Any Q
t
QFB
QFB
SK(PP)
Max. skew
Common
Device 1
Device 1
Device 2
Device2
= t
(∅)
+ t
Table 8.Confidence Factor
SK(O)
t
JIT(∅)
—t(ý)
+t
+ t
SK(O)
PD, LINE(FB)
+t
(∅)
t
JIT(∅)
t
SK(PP)
+ t
t
JIT(∅)
+t
PD,LINE(FB)
SK(O)
CF.
MPC961P
· CF
NETCOM
MPC961P
497