pc8477b National Semiconductor Corporation, pc8477b Datasheet - Page 6

• Manufacturer Part Number: pc8477b
• Description: Advanced Floppy Disk Controller
• Manufacturer: National Semiconductor Corporation

A0
A1
A2
AVCC
CS
D0
D1
D2
D3
D4
D5
D6
D7
DACK
DENSEL
DIR
DR0
DR1
DR2
DR3
DRQ
DRV2
DSKCHG
GND
GNDA
DRATE0
DRATE1
Symbol
2 0 Pin Description
16 21
36 50
54 59
PLCC
9 12
Pin
10
46
11
13
14
15
17
19
20
22
49
56
58
62
64
67
28
29
24
30
31
65
45
7
8
6
3
10 11
12 14
15 20
24 29
PQFP
Pin
44
45
46
17
43
47
48
49
50
52
54
55
56
40
19
26
28
32
34
36
58
51
16
2
3
4
5
I O
I O
O
O
O
O
O
I
I
I
I
I
Address These address lines from the microprocessor determine which internal FDC
register is accessed See TABLE 3-1 in the Register Description section A0 – A2 are don’t
cares during a DMA transfer
Analog Supply This pin is the 5V supply for the analog data separator
Chip Select Active low input from address decoder used to enable the RD and WR inputs
during register I O Should be held inactive during DMA transfers
Data Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB
These signals all have 12 mA buffered outputs
DMA Acknowledge Active low input to acknowledge the DMA request and enable the RD
and WR inputs during a DMA transfer DACK should be held inactive high during normal read
or write accesses when CS is active When in PC-AT or Model 30 mode this signal is
enabled by bit D3 of the DOR When in PS 2 mode DAK is always enabled and bit D3 of the
DOR is reserved
Density Select Indicates when a high density data rate (500 kb s or 1 Mb s) or a low
density data rate (250 or 300 kb s) has been selected DENSEL is active high for high
density (5 25 drives) when IDENT is high and active low for high density (3 5 drives) when
IDENT is low DENSEL is also programmable via the Mode command (see Section 4 2 6)
Direction This output determines the direction of the head movement (active
inactive
Drive Select 0 – 3 These are the decoded drive select outputs that are controlled by Digital
Output Register bits D0 D1 The Drive Select outputs are gated by DOR bits 4 – 7
Data Rate 0 1 These outputs reflect the currently selected data rate (bits 0 and 1 in the
CCR or the DSR whichever was written to last) These pins are totem-pole buffered outputs
(6 mA sink 4 mA source)
DMA Request Active high output to signal the DMA controller that a data transfer is needed
When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS 2
mode DRQ is always enabled and bit D3 of the DOR is reserved
Drive2 This input indicates whether a second disk drive has been installed The state of this
pin is available from Status Register A in PS 2 mode
Disk Change The input indicates if the drive door has been opened The state of this pin is
available from the Digital Input register This pin can also be configured as the RGATE data
separator diagnostic input via the Mode command (see Section 4 2 6)
Ground
Analog Ground This is the analog ground for the data separator
e
step out) during a seek operation During read or writes DIR will be inactive
6
Function
e
step in