ics9342 Holt Integrated Circuits, Inc., ics9342 Datasheet - Page 2

• Manufacturer Part Number: ics9342
• Description: 133mhz Clock Generator Integrated Buffer Powerpc
• Manufacturer: Holt Integrated Circuits, Inc.

General Description
Pin Configuration
Third party brands and names are the property of their respective owners.
The ICS9342 generates all clocks required for high speed PowerPC RISC microprocessor systems. With a zero delay buffer
chip such as the ICS9112-17 multiple PCI clock outputs can be generated in phase with PCIREF.
Spread Spectrum may be enabled by driving the SS_EN# pin low. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9342
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
ICS9342
26, 31, 36, 41, 46
27, 32, 37, 42, 47
PIN NUMBER
18, 17, 16
48, 25
2,3
10
11
12
13
14
15
19
20
21
22
23
24
1
4
5
6
7
8
9
OUTSEL(1:0)
CPU_STOP#
PIN NAME
PCI_STO P#
OUT_D IV2
GNDCPU
VDDCPU
VDDREF
GNDREF
REF[1:0]
VDDPCI
GNDPCI
BOOST#
SS_EN#
PCIREF
VDDFP
GNDFP
FS (2:0)
PDFP#
VDDA
TEST#
VDD
GND
O UT
PD#
X1
X2
TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OU T
OU T
OU T
OU T
OU T
PER
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Ref(1:0), XTAL power supply, nominal 3.3V
Ground pin for the REF outputs
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318M Hz.
Pow ers down chip, active low .
3.3V power for the digital core.
Ground pin for the digital core.
Drives PCIREF to logic 0 level, when input low
Spread spectrum is turned on by driving this input low and turned off by
driving it high.
Pow er supply for PCIREF, nominal 3.3V.
Ground pin for PCIREF.
Frequency select pins.
3.3V power for the Fixed PLL core.
Ground pin for the Fixed PLL core.
3.3V O UT reference clock.
Logic input to select over clocking or under clocking frequencies.
(latched input)
3.3V 1/2 frequency OUT reference clock.
Pow ers down Fixed PLL. When driven to low, OUT and OUT_DIV2 clocks
will be stopped
3.3V power for the PLL core
Ground pin for CPU clocks.
3.3V power supply for CPU clocks.
14.318 M Hz reference clocks
Stops all CPUCLKs [11:0] at logic 0 level, w hen input low
Reference clock for PCI Zero Delay Buffer.
Logic input to select normal or test mode frequencies. (latched input)
Frequency select pins for OUT and OUT_DIV2 clocks.
DESCRIPTION