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s29jl064h Summary of contents
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... Memory Data Sheet For new designs involving Fine-pitch Ball Grid Array (FBGA) packages, S29PL064J supersedes S29JL064H and is the factory recommended migration path. Please refer to the S29PL-J Data Sheet for specifications and ordering information. Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein ...
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... However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S29JL064H S29JL064H_00_A7 September 19, 2007 ...
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... High Performance – Access time as fast – Program time: 4 µs/word typical using accelerated programming function Publication Number S29JL064H_00 Ultra Low Power Consumption (typical values) – active read current at 1 MHz – active read current at 5 MHz – 200 nA in standby or automatic sleep mode ...
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... Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Simultaneous Read/Write Operations with Zero Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 S29JL064H Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8. Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2 Requirements for Reading Array Data ...
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... TS 048—48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 21. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 21.1 Revision A (January 22, 2004 21.2 Revision A1 (March 26, 2004 21.3 Revision A 2 (April 28, 2004 21.4 Revision A3 (September 16, 2004 21.5 Revision A4 (June 28, 2005 21.6 Revision A5 (June 6, 2007 21.7 Revision A6 (August 10, 2007 21.8 Revision A7 (September 19, 2007 September 19, 2007 S29JL064H_00_A7 S29JL064H 5 ...
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... Figure 17.10 Toggle Bit Timings (During Embedded Algorithms Figure 17.11 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 17.12 Temporary Sector Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 17.13 Sector/Sector Block Protect and Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 17.14 Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CC1 S29JL064H S29JL064H_00_A7 September 19, 2007 ...
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... S29JL064H Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8.2 S29JL064H Sector Architecture Table 8.3 Bank Address Table 8.4 Secured Silicon Sector Addresses Table 8.5 S29JL064H Autoselect Codes, (High Voltage Method Table 8.6 S29JL064H Boot Sector/Sector Block Addresses for Protection/Unprotection . . . . . . . . . . . 22 Table 8.7 WP#/ACC Modes Table 9.1 CFI Query Identification String Table 9.2 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9 ...
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... General Description The S29JL064H megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt V and can also be programmed in standard EPROM programmers ...
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... Power consumption is greatly reduced in both modes. 2. Product Selector Guide Speed Option Max Access Time (ns), t CE# Access (ns OE# Access (ns September 19, 2007 S29JL064H_00_A7 detector that automatically inhibits write operations CC Part Number Standard Voltage Range 2.7–3.6 V ACC ...
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... CE# COMMAND REGISTER BYTE# WP#/ACC DQ0–DQ15 A21–A0 Mux OE# BYTE# Bank 1 Bank 1 Address X-Decoder Bank 2 Address Bank 2 X-Decoder Status Control X-Decoder Bank 3 Bank 3 Address X-Decoder Bank 4 Address Bank 4 S29JL064H DQ15–DQ0 Mux S29JL064H_00_A7 September 19, 2007 ...
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... A17 Figure 4.2 63-Ball Fine-Pitch BGA (FBGA) - Top View, Balls Facing Down A8 B8 NC* NC NC* NC NC* NC* September 19, 2007 S29JL064H_00_A7 Figure 4.1 48-Pin Standard TSOP ...
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... V CC supply tolerances) V Device Ground SS NC Pin Not Connected Internally 6. Logic Symbol Product Selector Guide on page 9 22 A21–A0 DQ15–DQ0 (A-1) CE# OE# WE# WP#/ACC RESET# RY/BY# BYTE# S29JL064H for speed options and voltage S29JL064H_00_A7 September 19, 2007 ...
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... The order number is formed by a valid combinations of the following: S29JL064H 55 Note For new designs involving Fine-pitch Ball Grid Array (FBGA) packages, S29PL064J supersedes S29JL064H and is the factory recommended migration path. Please refer to the S29PL-J Data Sheet for specifications and ordering information. Device Family Speed Option ...
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... If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function Table 8.1 Table 8.1 S29JL064H Device Bus Operations WP#/ CE# OE# WE# RESET# ACC ...
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... If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Command Sequence on page 32 September 19, 2007 S29JL064H_00_A7 for timing specifications and to ...
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... RESET# parameters and to S29JL064H shows how read and write and I in the DC Characteristics CC6 CC7 ± 0 but not within CC5 ±0.3 V, the device SS ±0.3 V, the standby current SS (during Embedded Algorithms). The after the RH Figure 17.2 on page 47 for the timing S29JL064H_00_A7 September 19, 2007 ...
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... SA19 SA20 SA21 SA22 September 19, 2007 S29JL064H_00_A7 output from the device is disabled. The output pins are placed in the high IH Table 8.2 S29JL064H Sector Architecture (Sheet Sector Address Sector Size A21–A12 (Kbytes/Kwords) Address Range 0000000000 8/4 000000h–001FFFh ...
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... SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Table 8.2 S29JL064H Sector Architecture (Sheet Sector Address Sector Size A21–A12 (Kbytes/Kwords) Address Range 0010000xxx 64/32 100000h–10FFFFh 0010001xxx 64/32 110000h–11FFFFh 0010010xxx 64/32 120000h–12FFFFh ...
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... SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 September 19, 2007 S29JL064H_00_A7 Table 8.2 S29JL064H Sector Architecture (Sheet Sector Address Sector Size A21–A12 (Kbytes/Kwords) Address Range 1000000xxx 64/32 400000h–40FFFFh 1000001xxx 64/32 410000h–41FFFFh 1000010xxx 64/32 420000h–42FFFFh ...
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... SA141 Note The address range is A21:A-1 in byte mode (BYTE Bank Device S29JL064H Table 8.2 S29JL064H Sector Architecture (Sheet Sector Address Sector Size A21–A12 (Kbytes/Kwords) Address Range 1110000xxx 64/32 700000h–70FFFFh 1110001xxx 64/32 710000h–71FFFFh 1110010xxx 64/32 720000h– ...
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... To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Autoselect Command Sequence on page 32 Table 8.5 S29JL064H Autoselect Codes, (High Voltage Method) A21 Description CE# ...
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... The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. Table 8.6 S29JL064H Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet Sector SA0 ...
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... Table 8.6 S29JL064H Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet Sector SA131–SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 Sector protect/Sector Unprotect requires V system or via programming equipment. on page 54 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle ...
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... Figure 8.1 Temporary Sector Unprotect Operation START RESET (Note 1) Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed (Note 2) , sectors 0, 1, 140, and 141 will remain protected). IL S29JL064H Table 8.6 . During this mode, formerly ID is removed ID Figure 8.1 shows the S29JL064H_00_A7 September 19, 2007 ...
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... No Remove V ID from RESET# Write reset command Sector Protect Sector Protect complete Algorithm September 19, 2007 S29JL064H_00_A7 Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector ...
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... Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array Figure 8.2 on page 27. S29JL064H Enter Secured Silicon 32). After the system has written the Enter 25, except that RESET# may be at either S29JL064H_00_A7 September 19, 2007 ...
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... CE# and WE# must be a logical zero while OE logical one. 8.14.4 Power-Up Write Inhibit If WE and OE edge of WE#. The internal state machine is automatically reset to the read mode on power-up. September 19, 2007 S29JL064H_00_A7 Figure 8.3 Secured Silicon Sector Protect Verify START If data = 00h, RESET# = ...
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... Max. timeout per individual block erase 2 N 0000h Max. timeout for full chip erase 2 times typical (00h = not supported) S29JL064H to Table 9.4 on page 30. To Table 9.1 Description Description N µs µ (00h = not supported times typical S29JL064H_00_A7 September 19, 2007 ...
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... September 19, 2007 S29JL064H_00_A7 Table 9.3 Device Geometry Definition Data N 0017h Device Size = 2 byte 0002h Flash Device Interface description (refer to CFI publication 100) 0000h 0000h Max. number of byte in multi-byte write = 2 ...
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... Bank Organization 0004h 00 = Data at 4Ah is zero Number of Banks Bank 1 Region Information 0017h X = Number of Sectors in Bank 1 Bank 2 Region Information 0030h X = Number of Sectors in Bank 2 Bank 3 Region Information 0030h X = Number of Sectors in Bank 3 Bank 4 Region Information 0017h X = Number of Sectors in Bank 4 S29JL064H Description S29JL064H_00_A7 September 19, 2007 ...
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... If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). September 19, 2007 S29JL064H_00_A7 defines the valid register command sequences. Writing incorrect address for more information ...
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... See also for further information. Note that the ACC function shows the address and data requirements for the byte program command for information on these status bits. S29JL064H Table 8.3 S29JL064H_00_A7 September 19, 2007 ...
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... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 10.1 on page 33 Operations on page 49 Note 1. See Table 10.1 on page 36 September 19, 2007 S29JL064H_00_A7 36). illustrates the algorithm for the program operation. Refer to for parameters, and Figure 17.5 on page 50 Figure 10 ...
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... Refer to for parameters, and Figure 17.7 on page 51 S29JL064H shows the address and data requirements Erase and Program for timing diagrams. Table 10.1 on page 36 shows the for information on Erase and Program for timing diagrams. S29JL064H_00_A7 September 19, 2007 ...
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... To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. September 19, 2007 S29JL064H_00_A7 Figure 10 ...
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... The device ID must be read across the fourth, fifth, and sixth cycles. 10. The data is 81h for factory locked, 41h for customer locked, and 01h for not factory/customer locked Table 10.1 S29JL064H Command Definitions Bus Cycles (Notes 2–5) First Second Third ...
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... DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on successive read cycles. Table 11.1 on page 42 Polling algorithm. Figure 17.9 on page 52 September 19, 2007 S29JL064H_00_A7 and the following subsections describe the function of these bits. DQ7 shows the outputs for Data# Polling on DQ7. ...
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... Table 11.1 on page Figure 11.1 Data# Polling Algorithm START Read DQ7–DQ0 Addr = VA Yes DQ7 = Data DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA Yes DQ7 = Data? No FAIL . shows the outputs for RY/BY#. S29JL064H PASS S29JL064H_00_A7 September 19, 2007 ...
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... If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. September 19, 2007 S29JL064H_00_A7 37). ...
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... DQ6: Toggle Bit I on page 39. shows the differences between DQ2 and DQ6 in graphical form. S29JL064H Table 11.1 on page 42 to compare DQ2: Toggle Bit II on page 40 Figure 17.10 on page 52 shows the toggle bit S29JL064H_00_A7 September 19, 2007 ...
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... DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11.1 on page 42 September 19, 2007 S29JL064H_00_A7 for the following discussion. Whenever the system initially begins reading Figure 11 ...
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... V to +4.0 V –0 +12.5 V –0 +10.5 V –0 +0 200 mA to –2.0 V for periods of SS Figure 12.1 on page 42. During voltage transitions, input or I/O 42. 42. Maximum DC input voltage on pin S29JL064H_00_A7 September 19, 2007 RY/BY ...
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... active while Embedded Erase or Embedded Program is in progress Automatic sleep mode enables the low power mode when addresses remain stable for t 5. Not 100% tested. September 19, 2007 S29JL064H_00_A7 –40°C to +85° 3.6 V Test Conditions ...
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... Note ° Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 500 1000 1500 2000 Time in ns Figure 14.2 Typical I CC1 2 3 Frequency in MHz S29JL064H 2500 3000 3500 vs. Frequency 3 S29JL064H_00_A7 September 19, 2007 4000 5 ...
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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 16. Key To Switching Waveforms Waveform 3.0 V Input 0.0 V September 19, 2007 S29JL064H_00_A7 Figure 15.1 Test Setup Device Under Test C 6.2 kΩ L Table 15 ...
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... Speed Options Min CE#, Max Max Max Max 16 Max 16 Min 0 Min 0 Min 5 10 /2. The time from OE# high to the data bus HIGH Z Output Valid S29JL064H_00_A7 September 19, 2007 Unit ...
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... RESET# Low to Standby Mode RPD t RY/BY# Recovery Time RB Note Not 100% tested. RY/BY# CE#, OE# RESET# RY/BY# CE#, OE# RESET# September 19, 2007 S29JL064H_00_A7 Description (See Note) (See Note) (See Note) Figure 17.2 Reset Timings Ready Reset Timings NOT during Embedded Algorithms ...
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... AS and t specifications S29JL064H Speed Options Max 5 Max 16 Min Data Output Data (DQ14–DQ0) Output Address DQ15 Input Output t FLQZ Data Data Output (DQ14–DQ0) Address DQ15 Input Output t FHQV HOLD AH S29JL064H_00_A7 September 19, 2007 90 Unit ...
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... VCS BUSY Notes 1. Not 100% tested. 2. See Erase and Programming Performance on page 56 September 19, 2007 S29JL064H_00_A7 Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high ...
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... WPH A0h t is the true data at the program address. OUT Figure 17.6 Accelerated Program Timing Diagram IH t VHH S29JL064H Read Status Data (last two cycles WHWH1 Status D OUT t BUSY VHH S29JL064H_00_A7 September 19, 2007 IH ...
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... Addresses t AH CE# OE WE# t WPH Valid Data In WE# Controlled Write Cycle September 19, 2007 S29JL064H_00_A7 Figure 17.7 Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles 2AAh SA 555h for chip erase ...
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... Figure 17.10 Toggle Bit Timings (During Embedded Algorithms) t AHT t ASO t OEH t OEPH t OE Valid Valid Status Status (first read) (second read) S29JL064H VA True Valid Data True Valid Data Status Data AHT t CEPH Valid Status (stops toggling) S29JL064H_00_A7 September 19, 2007 High Z High Z Valid Data ...
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... RRB Sector Unprotect Note Not 100% tested RESET CE# WE# RY/BY# September 19, 2007 S29JL064H_00_A7 Figure 17.11 DQ2 vs. DQ6 Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Description V Rise and Fall Time (See Note) ID Rise and Fall Time ...
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... Sector Erase Operation (Note 2) Typ for more information. S29JL064H Valid* 40h Status Speed Options 0.4 S29JL064H_00_A7 September 19, 2007 Unit µs µs sec ...
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... Figure indicates last two bus cycles of a program or erase operation program address sector address program data. 3. DQ7# is the complement of the data written to the device Waveforms are for the word mode. September 19, 2007 S29JL064H_00_A7 555 for program ...
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... Excludes 00h programming prior to erasure (Note 4) sec µs µs µs Excludes system level overhead (Note 5) sec sec , 100,000 cycles; checkerboard data pattern. CC Table 10.1 Typ Max Unit TSOP 6 7.5 pF Fine-pitch BGA 4.2 5.0 pF TSOP 8 Fine-pitch BGA 5.4 6.5 pF TSOP 7 Fine-pitch BGA 3.9 4.7 pF S29JL064H_00_A7 September 19, 2007 ...
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... Physical Dimensions 20.1 FBE063—63-Ball Fine-Pitch Ball Grid Array (BGA package September 19, 2007 S29JL064H_00_A7 S29JL064H Dwg rev AF; 10/99 57 ...
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... TS 048—48-Pin Standard TSOP S29JL064H S29JL064H_00_A7 September 19, 2007 Dwg rev AA; 10/99 ...
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... Reformatted CMOS Compatible table columns. AC Characteristics Reformatted Erase and Program Operations table columns. 21.6 Revision A5 (June 6, 2007) Removed the 7 inch Tape and Reel Packing Type. 21.7 Revision A6 (August 10, 2007) DC Characteristics Changed V minimum, typical, and maximum values. LKO September 19, 2007 S29JL064H_00_A7 S29JL064H 59 ...
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... Revision A7 (September 19, 2007) S29JL064H Autoselect Codes, (High Voltage Method) Table Deleted code for 'customer locked' under column "DQ7 to DQ0" S29JL064H S29JL064H_00_A7 September 19, 2007 ...
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... Copyright © 2004-2007 Spansion Inc. All rights reserved. Spansion and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. September 19, 2007 S29JL064H_00_A7 ® ...