cldash-155.520 Raltron Electronics Corp., cldash-155.520 Datasheet

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cldash-155.520

Manufacturer Part Number
cldash-155.520
Description
Clock Oscillator, Lvds, +3.3 Vdc Or +2.5vdc
Manufacturer
Raltron Electronics Corp.
Datasheet
Operating temperature range
Storage temperature range
Supply voltage
Maximum Input Voltage
Maximum Output Voltage
Nominal Frequency
Supply Voltage
Supply Current
Output Logic Type
Load
Output Levels
Duty Cycle
Rise / Fall Time
Jitter
Phase Noise typ.
@155.52MHz
Overall Frequency Stability
Pin 1
CLD/CLDP SERIES: CLOCK OSCILLATOR, LVDS, +3.3 VDC or +2.5VDC
DESCRIPTION: A crystal controlled, high frequency, highly stable oscillator, adhering to Low Voltage
Differential Signaling (LVDS) Standards. The output can be Tri-stated to facilitate testing or combined multiple
clocks. The device is contained in a sub-miniature, very low profile, leadless ceramic SMD package with 6 gold
contact pads. This miniature oscillator is ideal for today's automated assembly environments.
$ $ $ $ ABSOLUTE MAXIMUM RATINGS:
$ $ $ $ ELECTRICAL PARAMETERS:
*1 Test Conditions Unless Stated Otherwise: Nominal Vcc, Nominal Load, +25 3 C
*2 Frequency Dependent
*3 Not All Stabilities Available With All Temperature Ranges—Please Consult Factory For Availability
APPLICATIONS AND FEATURES:
" Infiniband; 10GbE; Network Processors; SOHO Routing; Switches; WAN Interfaces
" Common Frequencies: 106.25 MHz; 125 MHz; 150 MHz; 155.52 MHz; 156.25 MHz; 161.1328 MHz
" +3.3 VDC or +2.5VDC LVDS
" Frequency Range from 50.000 to 315 MHz
" No multiplication
" Miniature Ceramic SMD Package Available on Tape and Reel
" Lead Free and ROHS Compliant
R A L T R O N E L E C T R O N I C S C O R P . ! 1 0 6 5 1 N . W . 1 9
PARAMETER
PARAMETER
Output Enabled
Output Disabled
phone: (305) 593-6033 ! fax: (305) 594-3973 ! e-mail: sales@raltron.com ! WEB: http://www.raltron.com
Ta
T(stg)
Vcc
Vi
Vo
SYMBOL
fo
Vcc
Is
Voh
Vol
Vod
VOS
OS
DC
tr / tf
J
£( f)
£( f)
£( f)
£( f)
En
Dis
SYMBO
f/fc
L
Connected between Out and Complementary Out
Output logic high
Output logic low
Differential output
Differential output error
Offset Voltage
Offset error
Measured at 50% of Vcc
Measured at 20/80% and 80/20% Vcc Levels
Integrated Phase tji RMS, Fj = 12 kHz…20 MHz
Integrated Phase RMS tii offset frequency 50KHz to
80MHz
Deterministic period Jitter tdj using wavecrest analyz.
Random period Jitter trj using wavecrest analyz.
Peak to Peak Jitter Tp-p using wavecrest analyz.
Op. Temp., Aging, Load, Supply and Cal. Variations
High Voltage or No Connect
Ground
f=10 Hz
f=1 KHz
f=10 KHz
f 100 KHz
TEST CONDITIONS
t h
Vss-0.5…Vcc+0.5
Vss-0.5…Vcc+0.5
*1
S t ! M i a m i , F l o r i d a 3 3 1 7 2 ! U . S . A .
-0.5…+5.0
-40…+85
-55…+90
VALUE
LVDS
100
1.43 Typ, 1.6 Max
0.9 Min, 1.10 Typ
1.125 Min, 1.25 Typ, 1.375 Max
50.000 ~ 315.00**
+3.3 or +2.5 5%
80.0 MAX
247 Min, 330 Typ, 454 Max
50 Max
50 Max
40/60 to 60/40 or 45/55 to 55/45
0.6 TYP
0.3 TYP**
0.5 TYP**
0.0TYP **
2.5 TYP **
25 TYP**
-120
-140
-145
0.7 Vcc MIN
0.3 Vcc MAX
-65
20, 25, 50, or 100 MAX
*2
VALUE
CLOCK
*3
Page 1 of 3
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
UNIT
VDC
VDC
VDC
UNIT
VDC
VDC
VDC
MHz
VDC
Ppm
VDC
VDC
mA
mV
mV
mV
ns
ps
ps
ps
ps
ps
C
C
%

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cldash-155.520 Summary of contents

Page 1

CLD/CLDP SERIES: CLOCK OSCILLATOR, LVDS, +3.3 VDC or +2.5VDC DESCRIPTION: A crystal controlled, high frequency, highly stable oscillator, adhering to Low Voltage Differential Signaling (LVDS) Standards. The output can be Tri-stated to facilitate testing or combined multiple clocks. The device ...

Page 2

... SERIES CLD: +3.3Vdc Clock with LVDS Comp. Output CLDP: +2.5Vdc Clock with LVDS Comp. Output EXAMPLE: CLDASH-155.520 Clock Oscillator, 7x5mm Package, +3.3 VDC Supply Voltage, LVDS Output, Standard Symmetry, 0…+70 C Operating Temperature Range, 50 ppm Total Frequency Stability, 155.520 MHz **Above 300MHz extended temp range and ±25ppm stability may not be available, jitter may vary upon spec requirements. ...

Page 3

REFLOW PROFILE: **ROHS COMPLIANT ...

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