isl90842 Intersil Corporation, isl90842 Datasheet - Page 7

• Manufacturer Part Number: isl90842
• Description: Quad Digitally Controlled Potentiometers Xdcp?
• Manufacturer: Intersil Corporation

Typical Performance Curves
Principles of Operation
The ISL90842 is an integrated circuit incorporating four
DCPs with their associated registers, and an I
interface providing direct communication between a host
and the DCPs.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer. The R
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal within the DCP is controlled by an 8-bit volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR<7:0>: 00h), its wiper
terminal (R
DCP contains all ones (WR<7:0>: FFh), its wiper terminal
(R
WR increases from all zeroes (00h) to all ones (255
decimal), the wiper moves monotonically from the position
furthest from R
the resistance between R
monotonically. Note that the R
not connected (left floating).
While the ISL90842 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates R
position which yields a rheostat setting that is about 1/2 of
R
The WRs can be read or written directly using the I
interface as described in the following sections. The I
interface Address Byte has to be set to 00h, 01h, 02h, and
03h to access the WR of DCP0, DCP1, DCP2, and DCP3,
respectively.
receiver pulls the SDA line LOW to acknowledge the
TOTAL
W
) is furthest from the R
.
FIGURE 7. FREQUENCY RESPONSE (2.2MHz)
TAP POSITION = MID POINT
R
TOTAL
W
) is closest to its R
H
=9.4K
OUTPUT
to a position closer to R
INPUT
W
pin of each DCP is connected to
H
H
and R
terminal. As the value of the
L
7
L
terminals for all four pots are
terminal. When the WR of a
W
decreases
H
. At the same time,
(Continued)
W
2
roughly at a
C serial
2
C serial
2
C
ISL90842
I
The ISL90842 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90842
operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 9). On power-up of the ISL90842 the SDA pin is in the
input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90842 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 9). A START condition is ignored during the power-up
of the device.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 9). A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
reception of the eight bits of data (See Figure 10).
2
C Serial Interface
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
FIGURE 8. LARGE SIGNAL SETTLING TIME
SCL
2
C interface is conducted by
SIGNAL AT WIPER
(WIPER UNLOADED
MOVEMENT FROM
ffh TO 00h)
January 16, 2006
FN8096.1