mach110-24ji Lattice Semiconductor Corp., mach110-24ji Datasheet - Page 6

• Manufacturer Part Number: mach110-24ji
• Description: High-density Ee Cmos Programmable Logic
• Manufacturer: Lattice Semiconductor Corp.

FUNCTIONAL DESCRIPTION
The MACH110 consists of two PAL blocks connected by
a switch matrix. There are 32 I/O pins and 6 dedicated
input pins feeding the switch matrix. These signals are
distributed to the two PAL blocks for efficient design
implementation. There are two clock pins that can also
be used as dedicated inputs.
The PAL Blocks
Each PAL block in the MACH110 (Figure 1) contains a
64-product-term logic array, a logic allocator, 16 macro-
cells and 16 I/O cells. The switch matrix feeds each PAL
block with 22 inputs. This makes the PAL block look
effectively like an independent “PAL22V16”.
There are four additional output enable product terms in
each PAL block. For purposes of output enable, the 16
I/O cells are divided into 2 banks of 8 macrocells. Each
bank is allocated two of the output enable product terms.
An asynchronous reset product term and an asynchro-
nous preset product term are provided for flip-flop
initialization. All flip-flops within the PAL block are
initialized together.
The Switch Matrix
The MACH110 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 16 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.
The Product-Term Array
The MACH110 product-term array consists of 64
product terms for logic use, and 6 special-purpose
product terms. Four of the special-purpose product
terms provide programmable output enable, one
provides asynchronous reset, and one provides a
synchronous preset. Two of the output enable product
terms are used for the first eight I/O cells; the other two
control the last eight macrocells.
The Logic Allocator
The logic allocator in the MACH110 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to
12 product terms. The design software automatically
configures the logic allocator when fitting the design into
the device.
Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
6
MACH110-12/15/20
The Macrocell
The MACH110 macrocells can be configured as either
registered or combinatorial, with programmable polar-
ity. The macrocell provides internal feedback whether
configured as registered or combinatorial. The flip-flops
can be configured as D-type or T-type, allowing for
product-term optimization.
The flip-flops can individually select one of two clock
pins, which are also available as data inputs. The regis-
ters are clocked on the LOW-to-HIGH transition of the
clock signal. The flip-flops can also be asynchronously
initialized with the common asynchronous reset and
preset product terms.
The I/O Cell
The I/O cell in the MACH110 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to eight I/O cells. Within each
PAL block, two product terms are available for selection
by the first eight three-state outputs; two other product
terms are available for selection by the last eight
three-state outputs.
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
Output Macrocell
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Table 1. Logic Allocation
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
0
0
1
2
3
4
5
6
8
8
9
10
11
12
13
14
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
Available
Clusters
1
1
2
3
4
5
6
7
9
9
10
, C
, C
, C
, C
, C
, C
, C
11
12
13
14
15
, C
, C
, C
, C
, C
2
3
4
5
6
7
10
11
12
13
14
15