st25e64 STMicroelectronics, st25e64 Datasheet - Page 9

• Manufacturer Part Number: st25e64
• Description: Serial Extended Addressing Compatible With I2c Bus 64k 8k X 8 Eeprom
• Manufacturer: STMicroelectronics

gram cycle. This STOP condition will trigger an
internal memory program cycle only if the STOP
condition is internally decoded right after the ACK
bit; any STOP condition decoded out of this ”10th
bit” time slot will not trigger the internal program-
ming cycle. All inputs are disabled until the comple-
tion of this cycle and the ST24/25E64 will not
respond to any request.
Minimizing System Delay by Polling On ACK.
During the internal Write cycle, the ST24/25E64
disable itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the Write time (t
AC Characteristics table, this timing value may be
reduced by an ACK polling sequence issued by the
master.
Figure 7. Write Cycle Polling using ACK
First byte of instruction
with RW = 0 already
decoded by ST24xxx
ReSTART
STOP
NO
W
NO
DEVICE SELECT
) is given in the
START Condition
WRITE Cycle
Addressing the
with RW = 0
in Progress
Operation is
Returned
Memory
ACK
Next
YES
WRITE Operation
Proceed
YES
The sequence is:
– Initial condition: a Write is in progress (see Fig-
– Step 1: the Master issues a START condition
– Step 2: if the ST24/25E64 are internally writ-
ure 7).
followed by a Device Select byte. (1st byte of
the new instruction)
ing, no ACK will be returned. The Master goes
back to Step1. If the ST24/25E64 have termi-
nated the internal writing, it will issue an ACK.
The ST24/25E64 are ready to receive the sec-
ond part of the instruction (the first byte of this
instruction was already sent during Step1).
Byte Address
Send
Random Address
READ Operation
Proceed
ST24E64, ST25E64
AI01099B
9/16