st25e64 STMicroelectronics, st25e64 Datasheet - Page 11

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st25e64

Manufacturer Part Number
st25e64
Description
Serial Extended Addressing Compatible With I2c Bus 64k 8k X 8 Eeprom
Manufacturer
STMicroelectronics
Datasheet

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Figure 9. Write Modes Sequence with Write Control = 1
sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont’d)
PAGE WRITE
(cont’d)
NO ACK
DEV SEL
DEV SEL
DATA IN N
R/W
R/W
ACK
ACK
NO ACK
BYTE ADDR
BYTE ADDR
ACK
ACK
counter will ’roll-over’ and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25E64 wait for an acknowledge during
the 9th bit time. If the master does not pull the SDA
line low during this time, the ST24/25E64 terminate
the data transfer and switch to a standby state.
BYTE ADDR
BYTE ADDR
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
ST24E64, ST25E64
DATA IN 2
AI01120
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