ds2152 Maxim Integrated Products, Inc., ds2152 Datasheet - Page 82

• Manufacturer Part Number: ds2152
• Description: Ds2152 Enhanced T1 Single Chip Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Figure 16-5. Receive Side 2.048MHz Boundary Timing (with Elastic Store
Enabled)
Figure 16-6. Transmit Side D4 Timing
NOTE 1: RSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO 1.
NOTE 2: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0).
NOTE 3: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1).
NOTE 4: RCHBLK IS FORCED TO 1 IN THE SAME CHANNELS AS RSER (SEE NOTE 1).
NOTE 5: THE F-BIT POSITION IS PASSED THROUGH THE RECEIVE SIDE ELASTIC STORE.
NOTE 6: RCHCLK DOES NOT TRANSITION HIGH IN THE CHANNELS IN WHICH THE RSER DATA IS FORCED TO 1 (SEE NOTE 1).
NOTE 1: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TCR2.4 = 0).
NOTE 2: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TCR2.4 = 1).
NOTE 3: TSYNC IN THE MULTIFRAME MODE (TCR2.3 = 1).
NOTE 4: TLINK DATA (FS BITS) IS SAMPLED DURING THE F-BIT POSITION OF EVEN FRAMES FOR INSERTION INTO THE OUTGOING
T1 STREAM WHEN ENABLED VIA TCR1.2.
NOTE 5: TLINK AND TLCLK ARE NOT SYNCHRONOUS WITH TSSYNC.
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