ds2152 Maxim Integrated Products, Inc., ds2152 Datasheet - Page 61
![no-image](/images/no-image-200.jpg)
ds2152
Manufacturer Part Number
ds2152
Description
Ds2152 Enhanced T1 Single Chip Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2152.pdf
(97 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ds2152L
Manufacturer:
724853-0
Quantity:
469
Part Number:
ds2152L
Manufacturer:
DALLAS
Quantity:
20 000
FDLS: FDL STATUS REGISTER (Address = 01 Hex)
Note: The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
(MSB)
RBOC
SYMBOL
TMEND
RHALF
THALF
RBOC
RNE
TNF
RPE
RPS
RPE
POSITION
FDLS.7
FDLS.6
FDLS.5
FDLS.4
FDLS.3
FDLS.2
FDLS.1
FDLS.0
RPS
NAME AND DESCRIPTION
Receive BOC Detector Change of State. Set whenever the
BOC detector sees a change of state from a BOC Detected to a
No Valid Code seen or vice versa. The setting of this bit prompt
the user to read the RBOC register for details.
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as a
CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RPRM register for details.
Receive Packet Start. Set when the HDLC controller detects an
opening byte. The setting of this bit prompts the user to read the
RPRM register for details.
Receive FIFO Half Full. Set when the receive 16-byte FIFO
fills beyond the halfway point. The setting of this bit prompts the
user to read the RPRM register for details.
Receive FIFO Not Empty. Set when the receive 16-byte FIFO
has at least 1 byte available for a read. The setting of this bit
prompts the user to read the RPRM register for details.
Transmit FIFO Half Empty. Set when the transmit 16-byte
FIFO empties beyond the halfway point. The setting of this bit
prompts the user to read the TPRM register for details.
Transmit FIFO Not Full. Set when the transmit 16-byte FIFO
has at least 1 byte available. The setting of this bit prompts the
user to read the TPRM register for details.
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this bit
prompts the user to read the TPRM register for details.
RHALF
61 of 97
RNE
THALF
TNF
TMEND
(LSB)