MX29LV640BU Macronix International, MX29LV640BU Datasheet - Page 17

• Manufacturer Part Number: MX29LV640BU
• Description: 64M-BIT [4M x 16] CMOS EQUAL SECTOR FLASH MEMORY
• Manufacturer: Macronix International

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MX29LV640BU
LOW VCC WRITE INHIBIT
When VCC is less than VLKO the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional write
when VCC is greater than VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE# or WE# will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL, CE#
= VIH or WE# = VIH. To initiate a write cycle CE# and
WE# must be a logical zero while OE# is a logical one.
POWER-UP SEQUENCE
The MX29LV640BU powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
POWER-UP WRITE INHIBIT
If WE#=CE#=VIL and OE#=VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to the read mode on power-up.
POWER SUPPLY DE COUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.
P/N:PM1081
REV. 1.0, MAR. 08, 2005
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