LTC3738 Linear Technology, LTC3738 Datasheet - Page 24

• Manufacturer Part Number: LTC3738
• Description: 3-Phase Buck Controller
• Manufacturer: Linear Technology

w w w . D a t a S h e e t 4 U . c o m
APPLICATIO S I FOR ATIO
LTC3738
If the duty cycle falls below what can be accommodated by
the minimum on-time, the IC will begin to skip every other
cycle, resulting in half-frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.
The minimum on-time for the IC is generally about 120ns.
However, as the peak sense voltage decreases the mini-
mum on-time gradually increases. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current equal to or greater than 30%
of I
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
24
%Efficiency = 100% – (L1 + L2 + L3 + ...)
OUT(MAX)
OUT
OUT
to its steady-state value. During this recovery
at V
, generating the feedback error signal that
IN(MAX)
LOAD
U
OUT
• ESR, where ESR is the effective
.
. ∆I
U
LOAD
also begins to charge or
W
OUT
shifts by an
U
time, V
ringing, which would indicate a stability problem. The
availability of the I
control loop behavior, but also provides a DC coupled
and AC filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly
second order system, phase margin and/or damping
factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The I
ponents shown in the Figure 1 circuit will provide an
adequate starting point for most applications.
The I
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2µs will produce output voltage and I
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the I
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R
increased by decreasing C
factor that C
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over-
all supply performance.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
TH
OUT
OUT
series R
, causing a rapid drop in V
can be monitored for excessive overshoot or
C
C
is decreased, the zero frequency will be kept
and the bandwidth of the loop will be
C
-C
TH
C
pin not only allows optimization of
filter sets the dominant pole-zero
C
TH
. If R
pin signal which is in the
C
is increased by the same
OUT
. No regulator can
TH
TH
pin waveforms
external com-
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