LTC1405 Linear Technology, LTC1405 Datasheet - Page 12

• Manufacturer Part Number: LTC1405
• Description: 12-Bit/ 5Msps/ Sampling ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC1405
are present. The SNR performance of an ADC when the
performance is limited by jitter is given by:
where f
the root-mean-square jitter due to the clock, the analog
input and the A/D aperture jitter. To minimize clock jitter,
use a clean clock source such as a crystal oscillator, treat
the clock signals as sensitive analog traces and use
dedicated packages with good supply bypassing for any
clock drivers.
Board Layout
To obtain the best performance from the LTC1405, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.
An analog ground plane separate from the logic system
ground should be placed under and around the ADC.
Pins 6, 8 and 24 (GND), Pin 21 (OGND) and all other
analog grounds should be connected to this ground plane.
In single supply mode, Pin 25 (V
12
CIRCUITRY
ANALOG
INPUT
IN
SNR = – 20log (2 f
is the frequency of an input sine wave and t
+
–
1000pF
U
1
+A
2
IN
U
–A
IN
BYPASS CAPACITORS
PLACE NON-GROUND
GROUND PLANE AND
IN
t
VIAS AWAY FROM
J
)dB
V
CM
Figure 13. Cross Section of LTC1405 Printed Circuit Board
3
W
1 F
SS
) should also be
V
REF
5
1 F
Figure 12. Power Supply Grounding
ANALOG GROUND PLANE
GND
U
6
AVOID BREAKING GROUND PLANE
J
V
DD
is
7
1 F
LTC1405
IN THIS AREA
LTC1405
GND
connected to this ground plane. All bypass capacitors for
the LTC1405 should also be connected to this ground
plane (Figure 12). The digital system ground should be
connected to the analog ground plane at only one point,
near the OGND pin.
The analog ground plane should be as close to the ADC as
possible. Care should be taken to avoid making holes in the
analog ground plane under and around the part. To ac-
complish this, we recommend placing vias for power and
signal traces outside the area containing the part and the
decoupling capacitors (Figure 13).
Supply Bypassing
High quality, low series resistance ceramic 1 F capacitors
should be used at both V
connected to – 5V it should also be bypassed to ground
with 1 F. In single supply operation V
to the ground plane as close to the part as possible. If OV
is not shorted to Pin 23 (V
decoupling capacitor to ground. Surface mount capaci-
tors such as the AVX 0805ZC105KAT provide excellent
bypassing in a small board space. The traces connecting
the pins and the bypass capacitors must be kept short and
should be made as wide as possible.
8
V
DD
23
1 F
OV
DD
22
1 F
GND
BYPASS
CAPACITOR
ANALOG
GROUND
PLANE
24
1405 F13
DD
pins, V
V
SS
DD
25
1 F
) it also requires a 1 F
OGND
CM
SS
21
and V
should be shorted
REF
SYSTEM
DIGITAL
. If V
1405 F12
SS
DD
is