LTC1405 Linear Technology, LTC1405 Datasheet

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LTC1405

Manufacturer Part Number
LTC1405
Description
12-Bit/ 5Msps/ Sampling ADC
Manufacturer
Linear Technology
Datasheet

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FEATURES
APPLICATIO S
TYPICAL APPLICATIO
, LTC and LT are registered trademarks of Linear Technology Corporation.
Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectral Analysis
Imaging Systems
5Msps Sample Rate
Low Power Dissipation: 115mW
Single 5V Supply or 5V Supplies
Integral Nonlinearity Error <0.35LSB
Differential Nonlinearity <0.25LSB
71.3dB S/(N + D) and 85dB SFDR at Nyquist
100MHz Full-Power Bandwidth Sampling
Input PGA
Out-of-Range Indicator
True Differential Inputs with 75dB CMRR
28-Pin Narrow SSOP Package
Pin-Compatible 10Msps Version (LTC1420)
2.048V, 1.024V and 0.512V Bipolar Input Range
SENSE
+
–A
V
V
A
REF
CM
IN
IN
1 F
1 F
1 F
0V OR –5V
MODE SELECT
U
V
SS
5V
S/H
GAIN
1 F
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the
interconnection of its circuits as described herein will not infringe on existing patent rights.
2.048V
AGND
PIPELINED 12-BIT ADC
DIGITAL CORRECTION
5V
REFERENCE
U
AV
2.5V
DD
LOGIC
1 F
5V
DGND
DV
DD
BUFFERS
OUTPUT
OV
OGND
DD
1 F
1405 TA01
OPTIONAL 3V
LOGIC SUPPLY
OF
D11 (MSB)
D0 (LSB)
5MHz CLK
DESCRIPTIO
The LTC
that draws only 115mW from either single 5V or dual 5V
supplies. This easy-to-use device includes a high dynamic
range sample-and-hold, a precision reference and a PGA
input circuit.
The LTC1405 has a flexible input circuit that allows full-
scale input ranges of 2.048V, 1.024V and 0.512V. The
input common mode range is rail-to-rail and a common
mode bias voltage is provided for single supply applica-
tions. The input PGA has a digitally selectable 1x or 2x
gain.
Maximum DC specs include 1LSB INL and 1LSB DNL
over temperature. Outstanding AC performance includes
71.3dB S/(N + D) and 85dB SFDR at the Nyquist input
frequency of 2.5MHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 100MHz
bandwidth. The 75dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source. A
separate output logic supply allows direct connection to
3V components.
®
1405 is a 5Msps, 12-bit sampling A/D converter
U
–0.25
–0.50
–0.75
–1.00
1.00
0.75
0.50
0.25
Final Electrical Specifications
0
0
Sampling ADC
12-Bit, 5Msps,
Typical INL Curve
1024
CODE
2048
January 2000
LTC1405
3072
1405 TA02
4096
1

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LTC1405 Summary of contents

Page 1

... This easy-to-use device includes a high dynamic range sample-and-hold, a precision reference and a PGA input circuit. The LTC1405 has a flexible input circuit that allows full- scale input ranges of 2.048V, 1.024V and 0.512V. The input common mode range is rail-to-rail and a common mode bias voltage is provided for single supply applica- tions ...

Page 2

... Digital Output Voltage ........ (V – 0.3V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1405C ............................................... LTC1405I ............................................ – Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 VERTER CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T With Internal 4 ...

Page 3

... C. Specifications are guaranteed for both dual supply and single supply A CONDITIONS V = 5.25V 5.25V – 4.75V 4.75V – LTC1405 MIN TYP MAX – 250 0 4.096V – 0.1dBFS single ended input, REF IN MIN TYP MAX 69.0 71.6 68.7 71.3 – 87 – 78.5 – 83 – 77.0 – 89 – ...

Page 4

... LTC1405 U U DIGITAL I PUTS AND OUTPUTS temperature range, otherwise specifications are at T operation. (Note 5) SYMBOL PARAMETER I Digital Input Current IN C Digital Input Capacitance IN V High Level Output Voltage OH V Low Level Output Voltage OL I Output Source Current SOURCE I Output Sink Current ...

Page 5

... CLK (Pin 26): Conversion Start Signal. This active high signal starts a conversion on its rising edge. OF (Pin 27): Overflow Output. This signal is high when the digital output is 011111111111 or 100000000000. GAIN (Pin 28): Gain Select for Input PGA. 5V selects an input gain selects a gain of 2. LTC1405 ...

Page 6

... LTC1405 CTIO AL BLOCK DIAGRA – MODE SELECT SENSE V REF 0V OR – DIAGRA ANALOG INPUT CLK DATA OUTPUT GAIN (PIN 7) (PIN 23) S/H PIPELINED 12-BIT ADC DIGITAL CORRECTION LOGIC 2.5V REFERENCE 2.048V V GND GND GND SS (PIN 6) ...

Page 7

... Power Supplies The LTC1405 will operate from either a single 5V or dual 5V supply, making it easy to interface the analog input to single or dual supply systems. The digital output drivers have their own power supply pin (OV from 3V to 5V, allowing direct connection to either digital systems ...

Page 8

... For single 5V supply applications it is convenient to connect A V pin. CM Driving the Analog Inputs The differential inputs of the LTC1405 are easy to drive. The inputs may be driven differentially or single-ended – (i. e., the A input is held at a fixed value). The A IN ...

Page 9

... IN LTC1405 – 1405 F05 Figure 7. AC Coupling to the LTC1405. Note That the Input Signal Can Almost Always Be Directly Coupled with Better Performance LTC1405 – A COMMENTS IN 0 Best SNR, THD 2.5 Best SINAD, THD for Single Supply 2.5 Worse Noise than Above Case 2 ...

Page 10

... If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1405 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifica- tions are most critical and time domain applications where DC accuracy and settling time are most critical ...

Page 11

... Thus output data can be latched on the third CLK rising edge after the rising edge that samples the input. Clock Input The LTC1405 only uses the rising edge of the CLK pin for internal timing, and CLK doesn’t necessarily need to have a 50% duty cycle. For optimal AC performance the rise time of the CLK should be less than 5ns ...

Page 12

... Figure 13. Cross Section of LTC1405 Printed Circuit Board connected to this ground plane. All bypass capacitors for the LTC1405 should also be connected to this ground plane (Figure 12). The digital system ground should be connected to the analog ground plane at only one point, is near the OGND pin. ...

Page 13

... U U APPLICATIO S I FOR ATIO W U LTC1405 13 ...

Page 14

... LTC1405 U U APPLICATIO S I FOR ATIO Figure 15. Top Silkscreen Layer for LTC1405/LTC1420 Demo Board Figure 17. Ground Plane Layer for LTC1405/LTC1420 Demo Board Figure 16. Top Layer for LTC1405/LTC1420 Demo Board Figure 18. Power Plane Layer for LTC1405/LTC1420 Demo Board ...

Page 15

... U U APPLICATIO S I FOR ATIO Figure 19. Bottom Layer for LTC1405/LTC1420 Demo Board U TYPICAL APPLICATIO Single Supply, 5Msps, 12-Bit ADC with 3V Logic Outputs 30 ANALOG INPUT (2.5V 1.024V) 1000pF LTC1405 GAIN NPO – CLK 5MHz CLOCK ...

Page 16

... COMMENTS Pin Compatible with LTC1405 Best Dynamic Performance, SINAD = 72dB at Nyquist 55mW Power Dissipation, 72dB SINAD 0.05% Max Initial Accuracy, 5ppm/ C Max Drift 1405i LT/TP 0100 4K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2000 0.033 (0.838) REF 0.150 – ...

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