HEF4013BP,652 NXP Semiconductors, HEF4013BP,652 Datasheet - Page 7

• Manufacturer Part Number: HEF4013BP,652
• Description: IC FLIP FLOP DUAL D TYPE 14DIP
• Manufacturer: NXP Semiconductors
• Series: 4000Br
• Type: D-Typer

Specifications of HEF4013BP,652

• Package / Case: 14-DIP (0.300", 7.62mm)
• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 40MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 3.4mA, 3.4mA
• Voltage - Supply: 3 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Number Of Circuits: 2
• Logic Family: HE4000B
• Logic Type: D-Type Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 90 ns
• High Level Output Current: - 4.2 mA
• Low Level Output Current: 4.2 mA
• Supply Voltage (max): 15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 3 V
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Package Type: DIP
• Frequency (max): 40MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 15V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Through Hole
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1684-5; 933277610652; HEF4013BPN

NXP Semiconductors
Table 7.
T
[1]
Table 8.
V
12. Waveforms
HEF4013B_6
Product data sheet
Symbol Parameter
t
f
Symbol Parameter
P
rec
clk(max)
amb
SS
Fig 4.
D
= 0 V; t
Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. C
= 25 C; unless otherwise specified. For test circuit see
recovery time
maximum clock
frequency
Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in
Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
dynamic power dissipation
r
Dynamic characteristics
input nCP
output nQ
Dynamic power dissipation
= t
input nD
f
20 ns; T
V
V
0 V
0 V
OH
OL
V
V
I
I
amb
= 25 C.
Conditions
nSD input;
see
nCD input;
see
see
V
M
Figure 5
Figure 5
Figure 4
…continued
V
V
10 V P
15 V P
Table
1/f
t
M
su
5 V P
DD
clk(max)
t
h
9.
t
PLH
Typical formula
D
D
D
Rev. 06 — 27 October 2009
= 850
= 3600
= 9000
V
V
X
V
M
Y
t
t
V
10 V
15 V
10 V
15 V
10 V
15 V
5 V
5 V
5 V
DD
f
i
f
f
+ (f
i
i
t
Figure
+ (f
W
+ (f
t
su
o
o
o
t
C
6.
h
C
Extrapolation formula Min
C
L
)
L
L
)
)
t
PHL
V
t
t
V
DD
V
DD
DD
2
t
f
2
2
W
W
W
Where
f
f
C
V
i
o
(f
DD
= input frequency in MHz;
L
= output frequency in MHz;
o
= output load capacitance in pF;
t
r
= supply voltage in V.
C
L
+15
) = sum of the outputs;
15
15
40
25
25
14
20
7
HEF4013B
Dual D-type flip-flop
Typ
© NXP B.V. 2009. All rights reserved.
25
10
10
14
28
40
001aah016
5
0
0
Max
-
-
-
-
-
-
-
-
-
L
is given in pF.
Unit
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
7 of 15