MT8980DP1 Zarlink Semiconductor, Inc., MT8980DP1 Datasheet - Page 4

• Manufacturer Part Number: MT8980DP1
• Description: 256 x 256 Channels (8 TDM Streams at 2.048 Mbps) Non-blocking Digital Switch (DX)
• Manufacturer: Zarlink Semiconductor, Inc.

MT8980D
Functional Description
In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control.
been a trend in system architectures towards
distributed processing or multi-processor systems.
In accordance with these trends, Zarlink has devised
the ST-BUS (Serial Telecom Bus).
architecture can be used both in software-controlled
digital
interprocessor communications.
switching and in interprocessor communications are
completely integrated to allow for a simple general
purpose architecture appropriate for the systems of
the future.
The
continuously at 2048 kbit/s and are arranged in 125
µ s wide frames which contain 32 8-bit channels.
Zarlink manufactures a number of devices which
interface to the ST-BUS;
MT8980 chip.
The MT8980 can switch data from channels on ST-
BUS inputs to channels on ST-BUS outputs, and
simultaneously allows its controlling microprocessor
to read channels on ST-BUS inputs or write to
channels on ST-BUS outputs (Message Mode). To
the microprocessor, the MT8980 looks like a memory
peripheral.
MT8980 to establish switched connections between
input
channels, or to transmit messages on output ST-BUS
channels.
microprocessor can receive messages from ST-BUS
input channels or check which switched connections
have already been established.
By integrating both switching and interprocessor
communications, the MT8980 allows systems to use
distributed processing and to switch voice or data in
an ST-BUS architecture.
2-6
* Writing to the Control Register is the only fast transaction.
†
A5
Memory and stream are specified by the contents of the Control Register.
0
1
1
1
•
•
•
serial
ST-BUS
voice
A4
X
0
0
1
•
•
•
The microprocessor can write to the
By reading from the MT8980, the
streams
and
channels
A3
X
0
0
1
•
•
•
data
of
Simultaneously, there has
A2
X
0
0
1
•
•
•
a key device being the
the
and
switching,
A1
ST-BUS
X
0
0
1
•
•
•
output
The uses in
Figure 3- Address Memory Map
A0
X
0
1
1
This bus
•
•
•
and
ST-BUS
operate
HEX ADDRESS
for
00 - 1F
20
21
3F
•
•
•
Hardware Description
Serial data at 2048 kbit/s is received at the eight ST-
BUS inputs (STi0 to STi7), and serial data is
transmitted at the eight ST-BUS outputs (STo0 to
STo7). Each serial input accepts 32 channels of
digital data, each channel containing an 8-bit word
which may represent a PCM-encoded analog/voice
sample as provided by a codec (e.g., Zarlink’s
MT8964).
This serial input word is converted into parallel data
and stored in the 256 X 8 Data Memory. Locations in
the Data Memory are associated with particular
channels on particular ST-BUS input streams. These
locations can be read by the microprocessor which
controls the chip.
Locations in the Connection Memory, which is split
into high and low parts, are associated with
particular ST-BUS output streams. When a channel
is due to be transmitted on an ST-BUS output, the
data for the channel can either be switched from an
ST-BUS
microprocessor.
input, then the contents of the Connection Memory
Low location associated with the output channel is
used to address the Data Memory.
Memory address corresponds to the channel on the
input ST-BUS stream on which the data for switching
arrived. If the data for the output channel originates
from the microprocessor (Message Mode), then the
contents of the Connection Memory Low location
associated with the output channel are output
directly, and this data is output repetitively on the
channel once every frame until the microprocessor
intervenes.
The Connection Memory data is received, via the
Control Interface, at D7 to D0. The Control Interface
also receives address information at A5 to A0 and
handles
DTA, R/W and DS.
address in the Data Memory or Connection Memory.
input
the microprocessor
or
If the data is switched from an
it
Control Register *
There are two parts to any
Channel 31
can
LOCATION
Channel 0
Channel 1
•
•
•
originate
control signals CS,
†
†
†
This Data
from
the