IDT72V291L15PFI IDT, Integrated Device Technology Inc, IDT72V291L15PFI Datasheet - Page 13

• Manufacturer Part Number: IDT72V291L15PFI
• Description: IC FIFO SS 32768X36 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V291L15PFI

• Function: Synchronous
• Memory Size: 1.1M (32K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V291L15PFI

WCLK cycle.
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + t
further write operations. Upon the completion of a valid read cycle, IR will
go LOW allowing a write to occur. The IR flag is updated by two WCLK
cycles + t
mode.
READ CLOCK (RCLK)
read on the outputs, on the rising edge of the RCLK input. It is permissible to
stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF flags
will not be updated. (Note that RCLK is only capable of updating the HF flag
to HIGH.) The Write and Read Clocks can be independent or coincident.
READ ENABLE (REN
output register on the rising edge of every RCLK cycle if the device is not empty.
and no new data is loaded into the output register. The data outputs Q
maintain the previous data value.
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EF) will go LOW,
inhibiting further read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH allowing a read to occur. The
EF flag is updated by two RCLK cycles + t
goes to the outputs Q
after the first write. REN does not need to be asserted LOW. In order to access
all other words, a read must be executed using REN. The RCLK LOW to HIGH
transition after the last word has been read from the FIFO, Output Ready (OR)
will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read
operations. REN is ignored when the FIFO is empty.
SERIAL ENABLE (SEN
offset registers. The serial programming method must be selected during
Master Reset. SEN is always used in conjunction with LD. When these
lines are both LOW, data at the SI input can be loaded into the program
register one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
settings and no offsets are loaded. SEN functions the same way in both
IDT Standard and FWFT modes.
OUTPUT ENABLE (OE
data from the output register. When OE is HIGH, the output data bus (Q
into a high impedance state.
LOAD (LD
determines one of two default offset values (127 or 1,023) for the PAE and
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
When WEN is HIGH, no new data is written in the RAM array on each
To prevent data overflow in the IDT Standard mode, FF will go LOW,
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
A read cycle is initiated on the rising edge of the RCLK input. Data can be
When Read Enable is LOW, data is loaded from the RAM array into the
When the REN input is HIGH, the output register holds the previous data
In the IDT Standard mode, every word accessed at Q
In the FWFT mode, the first word written to an empty FIFO automatically
The SEN input is an enable used only for serial programming of the
When SEN is HIGH, the programmable registers retains the previous
When Output Enable is enabled (LOW), the parallel output buffers receive
This is a dual purpose pin. During Master Reset, the state of the LD input
LD
LD
LD
LD)
SKEW
SKEW
after the valid RCLK cycle.
after the RCLK cycle.
REN
REN
REN
REN)
n
SEN
SEN
SEN
SEN)
, on the third valid LOW to HIGH transition of RCLK+ t
OE
OE
OE
OE)
SKEW
after the valid WCLK cycle.
TM
n
, including the first
n
) goes
SKEW
0
-Q
n
13
PAF flags, along with the method by which these offset registers can be
programmed, parallel or serial. After Master Reset, LD enables write
operations to and read operations from the offset registers. Only the offset
loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel. A LOW on LD during Master
Reset selects a default PAE offset value of 07FH (a threshold 127 words
from the empty boundary), a default PAF offset value of 07FH (a threshold
127 words from the full boundary), and parallel loading of other offset
values. A HIGH on LD during Master Reset selects a default PAE offset
value of 3FFH (a threshold 1,023 words from the empty boundary), a default
PAF offset value of 3FFH (a threshold 1,023 words from the full boundary),
and serial loading of other offset values.
process of the flag offset values PAE and PAF. Pulling LD LOW will begin
a serial loading or parallel load or read of these offset values. See Figure 4,
Programmable Flag Offset Programming Sequence.
OUTPUTS:
FULL FLAG (FF
function is selected. When the FIFO is full, FF will go LOW, inhibiting further
write operations. When FF is HIGH, the FIFO is not full. If no reads are
performed after a reset (either MRS or PRS), FF will go LOW after D
writes to the FIFO (D = 65,536 for the IDT72V281 and 131,072 for the
IDT72V291). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard
Mode), for the relevant timing information.
LOW when memory space is available for writing in data. When there is no
longer any free space left, IR goes HIGH, inhibiting further write operations.
If no reads are performed after a reset (either MRS or PRS), IR will go
HIGH after D writes to the FIFO (D = 65,537 for the IDT72V281 and
131,073 for the IDT72V291) See Figure 9, Write Timing (FWFT Mode), for
the relevant timing information.
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
are double register-buffered outputs.
EMPTY FLAG (EF
(EF) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not empty.
See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing (IDT
Standard Mode), for the relevant timing information.
LOW at the same time that the first word written to an empty FIFO appears
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH
transition that shifts the last word from the FIFO memory to the outputs. OR
goes HIGH only with a true read (RCLK with REN = LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until OR goes LOW again. See Figure 10, Read Timing
(FWFT Mode), for the relevant timing information.
mode, OR is a triple register-buffered output.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
After Master Reset, the LD pin is used to activate the programming
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
In FWFT mode, the Input Ready (IR) function is selected. IR goes
The IR status not only measures the contents of the FIFO memory, but
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
In FWFT mode, the Output Ready (OR) function is selected. OR goes
EF/OR is synchronous and updated on the rising edge of RCLK.
FF
FF
FF
FF/IR IR IR IR IR)
EF
EF
EF/OR
EF
OR
OR
OR)
OR
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES