IDT72V271LA10PF IDT, Integrated Device Technology Inc, IDT72V271LA10PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V271LA10PF
• Description: IC FIFO SS 16384X18 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V271LA10PF

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 6.5ns
• Word Size: 9b
• Organization: 32Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V271LA10PF

PIN CONFIGURATIONS
DESCRIPTION (CONTINUED)
write controls. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
• The limitation of the frequency of one clock input with respect to the
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
NOTES:
1. DC = Don’t Care. Must be tied to GND or V
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
other has been removed. The Frequency Select pin (FS) has been
removed, thus it is no longer necessary to select which of the two clock
inputs, RCLK or WCLK, is running at the higher frequency.
to an empty FIFO to the time it can be read, is now fixed and short.
(The variable clock cycle counting delay associated with the latency
period found on previous SuperSync devices has been eliminated on
this SuperSync family.)
PIN 1
GND
GND
GND
GND
GND
GND
GND
GND
GND
WEN
DC
SEN
V
V
D8
D7
CC
CC
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
CC
, cannot be left open.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
STQFP (PP64-1, ORDER CODE: TF)
TQFP (PN64-1, ORDER CODE: PF)
TOP VIEW
2
communications, data communications and other applications that need to
buffer large amounts of data.
Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLK when WEN is asserted. The output port is controlled by a Read
Clock (RCLK) input and Read Enable (REN) input. Data is read from the
FIFO on every rising edge of RCLK when REN is asserted. An Output
Enable (OE) input is provided for three-state control of the outputs.
0 to fMAX with complete independence. There are no restrictions on the
frequency of one clock input with respect to the other.
SuperSync FIFOs are particularly appropriate for network, video, tele-
The input port is controlled by a Write Clock (WCLK) input and a Write
The frequencies of both the RCLK and the WCLK signals may vary from
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMMERCIAL AND INDUSTRIAL
4673 drw 02
TEMPERATURE RANGES
DNC
DNC
GND
DNC
DNC
V
DNC
DNC
DNC
GND
DNC
DNC
Q8
Q7
Q6
GND
CC
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
JANUARY 30, 2009