IDT72261LA20PF IDT, Integrated Device Technology Inc, IDT72261LA20PF Datasheet - Page 27

• Manufacturer Part Number: IDT72261LA20PF
• Description: IC FIFO 8192X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72261LA20PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 12ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 75mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72261LA20PF

© 2009
is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is t
3. Tf is the period of the ‘selected clock’.
4. T
5. Typical I
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc.The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RCLK
IDT has improved the performance of the IDT72261/72271 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part
DIFFERENCES BETWEEN THE IDT72261LA/72271LA AND IDT72261L/72271L
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
is the cycle period of the read clock.
SKEW3
CC1
(FWFT Mode)
Pin #3
First Word Latency
(IDT Standard Mode)
First Word Latency
(FWFT Mode)
Retransmit Latency
(IDT Standard Mode)
Retransmit Latency
I
I
Typical I
is based on V
CC1
CC2
.
Item
CC1
CC
(5)
= 5V, t
A
= 25C, f
DC (Don’t Care) - There is
RCLK. See note 1.
60ns
60ns
60ns
60ns
75mA
20mA
15 + 1.85*f
no restriction on WCLK and
S
= WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at f
3.3 VOLT CMOS SuperSync FIFO
16,384 x 9
32,768 x9
(2)
(2)
(2)
(2)
+ t
+ t
+ t
+ t
IDT72261LA
IDT72271LA
NEW PART
REF
REF
REF
REF
S
+ 0.02*C
+ 1 T
+ 2 T
+ 1 T
+ 2 T
RCLK
RCLK
RCLK
RCLK
L
*f
(4)
(4)
(4)
(4)
S
(mA)
FS (Frequency Select)
t
t
t
t
150mA
15mA
Not Given
FWL
FWL
RTF
RTF
27
1
2
1
2
= 14*Tf
= 14*Tf
= 10*Tf
= 10*Tf
ADDENDUM
OLD PART
IDT72261L
IDT72271L
(3)
(3)
(3)
(3)
+ 3T
+ 4T
+ 2T
+ 3T
™
RCLK
RCLK
RCLK
RCLK
(4)
(4)
(4)
(4)
(ns)
(ns)
(ns)
(ns)
In the LA part this pin must be tied
to either V
not toggle after reset.
First word latency in the LA part
is a fixed value, independent of
the frequency of RCLK or WCLK.
First word latency in the LA part
is a fixed value, independent of
the frequency of RCLK or WCLK.
Retransmit latency in the LA part
is a fixed value, independent of
the frequency of RCLK or WCLK.
Retransmit latency in the LA part
is a fixed value, independent of
the frequency of RCLK or WCLK.
Active supply current
Standby current
Typical I
S
/2, C
L
Comments
CC1
= Capacitive Load (in pF).
CC
Current calculation
or GND and must
IDT72261LA
IDT72271LA