IDT72230L10TP IDT, Integrated Device Technology Inc, IDT72230L10TP Datasheet - Page 9

• Manufacturer Part Number: IDT72230L10TP
• Description: IC FIFO 2KX8 SYNC 10NS 28DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72230L10TP

• Function: Synchronous
• Memory Size: 16K (2K x 8)
• Data Rate: 67MHz
• Access Time: 11.5ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.300", 7.62mm)
• Configuration: Dual
• Density: 16Kb
• Access Time (max): 6.5ns
• Word Size: 8b
• Organization: 2Kx8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PDIP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 28
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72230L10TP

NOTES:
1. t
2. If a write is performed on this rising edge of the Write Clock, there will be Full - 6 words in the FIFO when AF goes LOW.
NOTES:
1. t
2. If a read is performed on this rising edge of the Read Clock, there will be Empty - 6 words in the FIFO when AE goes LOW.
WCLK
WCLK
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
RCLK
RCLK
WEN
WEN
REN
REN
rising edge of WCLK is less than t
rising edge of RCLK is less than t
AE
SKEW2
SKEW2
AF
is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the current clock cycle. If the time between the rising edge of WCLK and the
is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the current clock cycle. If the time between the rising edge of RCLK and the
t
t
CLKH
CLKH
SKEW2
SKEW2
Empty+7
t
t
Full - 8 words in FIFO
ENS
SKEW2
, then AE may not change state until the next RCLK edge.
, then AF may not change state until the next WCLK edge.
t
ENS
(1)
t
CLKL
t
CLKL
t
ENH
t
ENH
Figure 9. Almost Empty Flag Timing
Figure 8. Almost Full Flag Timing
t
AE
(2)
9
t
AF
t
ENS
t
ENS
Empty+8
t
SKEW2
Full - 7 words in FIFO
(1)
COMMERCIAL TEMPERATURE RANGE
t
ENH
t
ENH
(2)
JANUARY 8, 2009
t
AF
t
AE
2680 drw 11
2680 drw10