IDT72230L10TP IDT, Integrated Device Technology Inc, IDT72230L10TP Datasheet - Page 6

• Manufacturer Part Number: IDT72230L10TP
• Description: IC FIFO 2KX8 SYNC 10NS 28DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72230L10TP

• Function: Synchronous
• Memory Size: 16K (2K x 8)
• Data Rate: 67MHz
• Access Time: 11.5ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.300", 7.62mm)
• Configuration: Dual
• Density: 16Kb
• Access Time (max): 6.5ns
• Word Size: 8b
• Organization: 2Kx8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PDIP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 28
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72230L10TP

NOTES:
1. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
2. The Clocks (RCLK, WCLK) can be free-running during reset.
NOTE:
1. t
D
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
WCLK
Q
EF, AE
RCLK
FF, AF
0
WEN
REN
0
rising edge of WCLK is less than t
WEN
- D
SKEW1
REN
- Q
FF
RS
7
7
is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the
SKEW1
t
SKEW1
, then FF may not change state until the next WCLK edge.
(1)
t
CLKH
t
t
t
t
WFF
RSF
RSF
RSF
t
RS
t
t
RSS
RSS
t
DATA IN VALID
CLK
Figure 3. Write Cycle Timing
Figure 2. Reset Timing
t
CLKL
t
DS
t
ENS
6
t
t
DH
ENH
t
t
RSR
RSR
t
WFF
OE = 1
OE = 0
COMMERCIAL TEMPERATURE RANGE
(1)
NO OPERATION
JANUARY 8, 2009
2680 drw 05
2680 drw 04