CY241V08A-12 Cypress Semiconductor, CY241V08A-12 Datasheet - Page 3

• Manufacturer Part Number: CY241V08A-12
• Description: Clock Generator with VCXO
• Manufacturer: Cypress Semiconductor

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4
Document #: 38-07676 Rev. **
Absolute Maximum Conditions
Supply Voltage (V
DC Input Voltage...................................... –0.5V to V
Storage Temperature (Non-condensing)..... –55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Pullable Crystal Specifications
Recommended Operating Conditions
DC Electrical Specifications
AC Electrical Specifications
F
C
R
R
DL
F
F
C
C
C
V
T
C
t
I
I
C
V
f
I
DC
ER
EF
Notes:
Parameter
Parameter
PU
OH
OL
∆XO
VDD
1.
2.
3.
NOM
3SEPHI
3SEPLO
A
DD
Parameter
VCXO
LNOM
1
3
0
0
1
LOAD
IN
/R
/C
Crystals that meet this specification includes: Ecliptek ECX-5808-27.000M
–115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less
board capacitance.
Not 100% tested.
[2]
1
1
Parameter
[3]
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance (ESR)
Ratio of third overtone mode ESR to
fundamental mode ESR
Crystal drive level
Third overtone separation from 3*F
Third overtone separation from 3*F
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
Output HIGH Current
Output LOW Current
Input Capacitance
VCXO Input Range
VCXO Pullability Range
Supply Current
Output Duty Cycle
Rising Edge Rate
Falling Edge Rate
DD
) ........................................–0.5 to +7.0V
Name
Description
Name
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Power-up time for all V
voltage (power ramps must be monotonic)
(V
DD
[1]
= 3.3V)
V
V
Except XIN, XOUT pins
Low Side
High Side
OH
OL
Duty Cycle is defined in Figure 1, 50% of V
Output Clock Edge Rate, Measured from 20%
to 80% of V
Output Clock Edge Rate, Measured from 80%
to 20% of V
NOM
NOM
= 0.5V, V
= V
[3]
DD
DD
DD
Description
+ 0.5
Parallel resonance, fundamental mode, AT
cut
Fundamental mode
Ratio used because typical R
much less than the maximum spec
No external series resistor assumed
High side
Low side
– 0.5V, V
pins to reach minimum specified
Description
DD
DD
DD
, C
, C
= 3.3V
LOAD
LOAD
Description
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) JESD22-A114-B ............ > 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
DD
= 3.3V
= 15 pF. See Figure 2.
= 15 pF. See Figure 2.
Comments
1
values are
Min.
115
12
12
–
0
–
–
DD
3.135
Min.
0.05
0
–
Min.
0.8
0.8
45
Min. Typ. Max.
Typ.
14.4
150
300
180
24
24
CY241V08A-12
–
–
–
3
–
–
–
–
–
–
–
Typ.
3.3
–
–
–
Typ.
1.4
1.4
50
27
14
18
–
–
–
–
–
–
–
Max.
–115
V
40
3.465
–
–
7
–
Max.
DD
500
Max.
70
15
–150
21.6
55
250
–
–
Page 3 of 6
25
–
–
–
–
–
7
Unit
ppm
ppm
mA
mA
mA
V/ns
V/ns
Unit
pF
Unit
MHz
Unit
ppm
ppm
V
ms
µW
°C
pF
%
pF
pF
V
fF
Ω
–
–