IDT72215LB25J IDT, Integrated Device Technology Inc, IDT72215LB25J Datasheet - Page 11

IC FIFO 512X18 SYNC 25NS 68-PLCC

IDT72215LB25J

Manufacturer Part Number
IDT72215LB25J
Description
IC FIFO 512X18 SYNC 25NS 68-PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT72215LB25J

Function
Synchronous
Memory Size
9.2K (512 x 18)
Data Rate
40MHz
Access Time
25ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Configuration
Dual
Density
9Kb
Access Time (max)
15ns
Word Size
18b
Organization
512x18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
LCC
Clock Freq (max)
40MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
60mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72215LB25J

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NOTE:
1. When t
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
WCLK
D
Q
Q
D
RCLK
0
0
0
0
The Latency Timing applies only at the Empty Boundary (EF = LOW).
WEN
WCLK
–D
–Q
RCLK
- D
- Q
LD
15
15
17
17
SKEW2
t
t
ENS
LOW
DS
t
CLKH
minimum specification, t
DATA WRITE 1
t
CLKH
PAE OFFSET
t
t
ENH
SKEW2
DATA IN OUTPUT REGISTER
t
CLK
t
CLK
t
t
FRL
ENS
ENS
t
t
t
DS
ENS
ENS
t
CLKL
(maximum) = t
t
FRL
(1)
t
UNKNOWN
CLKL
CLK
Figure 10. Write Programmable Registers
Figure 11. Read Programmable Registers
PAF OFFSET
t
t
t
REF
ENH
t
DH
ENH
+ t
t
SKEW2
A
Figure 9. Empty Flag Timing
. When t
SKEW2
11
PAE OFFSET
t
A
< minimum specification, t
TM
t
REF
t
ENS
t
DS
D
DATA WRITE 2
0
–D
FRL
PAF OFFSET
11
(maximum) = either 2*t
t
ENH
t
SKEW2
PAE OFFSET
DATA READ
COMMERCIAL AND INDUSTRIAL
t
FRL
TEMPERATURE RANGES
CLK
(1)
+ t
PAE OFFSET
OCTOBER 22, 2008
t
SKEW2
REF
or t
2766 drw 11
CLK
2766 drw 12
2766 drw 13
+ t
SKEW2
.

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