25C040-/P Microchip Technology, Inc., 25C040-/P Datasheet - Page 7

• Manufacturer Part Number: 25C040-/P
• Description: The 25AA040 is a 4K Bit Serial Electrically Erasable Prom With Memory Accessed Via a Simple Serial Peripheral Interface (SPI™) Compatible Serial Bus
• Manufacturer: Microchip Technology, Inc.

3.0
3.1
The 25XX040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25XX040 contains an 8-bit instruction register. The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. The CS pin must be low
and the HOLD pin must be high for the entire operation.
The WP pin must be held high to allow writing to the
memory array.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. The most signif-
icant address bit (A8) is located in the instruction byte.
All instructions, addresses, and data are transferred
MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other periph-
eral devices on the SPI bus, the user can assert the
HOLD input and place the 25XX040 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
3.2
The part is selected by pulling CS low. The 8-bit read
instruction with the A8 address bit is transmitted to the
25XX040 followed by the lower 8-bit address (A7
through A0). After the correct read instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin. The data
stored in the memory at the next address can be read
sequentially by continuing to provide clock pulses. The
internal address pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by raising the
CS pin (Figure 3-1).
TABLE 3-1:
Note: A
Instruction Name
2001 Microchip Technology Inc.
WRITE
WREN
WRSR
READ
RDSR
WRDI
8
FUNCTIONAL DESCRIPTION
Principles of Operation
Read Sequence
is the 9
th
INSTRUCTION SET
address bit necessary to fully address 512 bytes.
Instruction Format
0000 A
0000 A
0000 0100
0000 0110
0000 0101
0000 0001
8
8
011
010
25AA040/25LC040/25C040
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read status register
Write status register
3.3
Prior to any attempt to write data to the 25XX040, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX040. After all eight bits of the instruction are trans-
mitted, the CS must be brought high to set the write
enable latch. If the write operation is initiated immedi-
ately after the WREN instruction without CS being
brought high, the data will not be written to the array
because the write enable latch will not have been prop-
erly set.
Once the write enable latch is set, the user may pro-
ceed by setting the CS low, issuing a write instruction,
followed by the address, and then the data to be writ-
ten. Keep in mind that the most significant address bit
(A8) is included in the instruction byte. Up to 16 bytes
of data can be sent to the 25XX040 before a write cycle
is necessary. The only restriction is that all of the bytes
must reside in the same page. A page address begins
with
internal address counter reaches
clock continues, the counter will roll back to the first
address of the page and overwrite any data in the page
that may have been written.
For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the status register may
be read to check the status of the WIP, WEL, BP1 and
BP0 bits (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
XXXX 0000
th
Write Sequence
data byte has been clocked in. If CS is
Description
and ends with
XXXX 1111
XXXX 1111
DS21204C-page 7
and the
. If the