25C040-/P Microchip Technology, Inc., 25C040-/P Datasheet - Page 10

• Manufacturer Part Number: 25C040-/P
• Description: The 25AA040 is a 4K Bit Serial Electrically Erasable Prom With Memory Accessed Via a Simple Serial Peripheral Interface (SPI™) Compatible Serial Bus
• Manufacturer: Microchip Technology, Inc.

25AA040/25LC040/25C040
3.5
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX040 is busy with a write operation. When set to a
‘
in progress. This bit is read only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘
allows writes to the array, when set to a ‘
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the status
register. This bit is read only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are nonvolatile.
See Figure 3-6 for RDSR timing sequence.
FIGURE 3-6:
FIGURE 3-7:
DS21204C-page 10
1
X
7
’, a write is in progress, when set to a ‘
X
6
Read Status Register (RDSR)
5
X
4
X
SCK
SCK
CS
SO
CS
SO
READ STATUS REGISTER SEQUENCE
WRITE STATUS REGISTER SEQUENCE
SI
SI
BP1
3
0
0
0
0
BP0
0
0
2
1
1
high impedance
0
0
2
instruction
2
instruction
WEL
0
0
1
0
3
3
1
0
’, no write is
’, the latch
’, the latch
0
0
4
4
WIP
1
0
0
5
5
high impedance
0
0
6
6
1
1
7
7
7
7
8
8
3.6
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg-
ments of the array. The partitioning is controlled as
illustrated in Table 3-2.
See Figure 3-7 for WRSR timing sequence.
TABLE 3-2:
6
6
9
data from status register
9
BP1
data to status register
0
0
1
1
10
10
5
5
Write Status Register (WRSR)
11
11
4
4
12
3
12
3
ARRAY PROTECTION
BP0
0
1
0
1
13
2
13
2
2001 Microchip Technology Inc.
14
14
1
1
15
0
15
0
Array Addresses
Write Protected
(0180h - 01FFh)
(0100h - 01FFh)
(0000h - 01FFh)
upper 1/4
upper 1/2
none
all