CY7C4245-15JXC Cypress Semiconductor Corp, CY7C4245-15JXC Datasheet - Page 11

• Manufacturer Part Number: CY7C4245-15JXC
• Description: IC SYNC FIFO MEM 4KX18 68-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245-15JXC

• Access Time: 10ns
• Memory Size: 72K (4K x 18)
• Package / Case: 68-PLCC
• Function: Synchronous
• Data Rate: 100MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 4 K x 18
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 45 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Waveforms
Notes:
Document Number: 001-45652 Rev. **
19. t
20. The clocks (RCLK, WCLK) can be free-running during reset.
21. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
REN, WEN,
Q
0
EF,PAE
FF,PAF,
Q
WCLK
–Q
RCLK
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
WEN
REN
0
–Q
OE
EF
17
RS
HF
LD
17
t
ENS
t
OLZ
(continued)
t
ENH
t
CLKH
t
t
A
REF
t
t
t
RSF
RSF
RSF
t
OE
t
RS
Figure 7. Read Cycle Timing
t
Figure 8. Reset Timing
CLK
t
SKEW2
NO OPERATION
SKEW2
[19]
t
CLKL
, then EF may not change state until the next RCLK edge.
[20]
VALID DATA
t
RSR
t
REF
t
OHZ
CY7C4425/4205/4215
CY7C4225/4235/4245
OE = 0
OE = 1
[21]
Page 11 of 22
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