NCP5314 ON Semiconductor, NCP5314 Datasheet - Page 20

• Manufacturer Part Number: NCP5314
• Description: Two/Three/Four-Phase Buck CPU Controller
• Manufacturer: ON Semiconductor

inductor of value Lo:
current is then:
I CIN,RMS + [4D @ (I C,MIN 2 ) I C,MIN @ DI C,IN
RMS input current (I
current rating per capacitor (I
the worst case input ripple−current will occur when the
converter is operating at a 12.5% duty cycle. At this
operating point, the parallel combination of input capacitors
must support an RMS ripple current equal to 12.5% of the
converter’s DC output current. At other duty cycles, the
ripple−current will be less. For example, at a duty cycle of
either 6% or 19%, the four−phase input ripple−current will
be approximately 10% of the converter’s DC output current.
specified ripple−current based on the ambient temperature.
More capacitors will be required because of the current
derating. The designer should know the ESR of the input
capacitors. The input capacitor power loss can be calculated
from:
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10 C rise in the
capacitor’s temperature.
5. Input Inductor Selection
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
For the four−phase converter, the input capacitor(s) RMS
Select the number of input capacitors (N
For a four−phase converter with perfect efficiency ( = 1),
In general, capacitor manufacturers require derating to the
Low ESR capacitors are recommended to minimize losses
The use of an inductor between the input capacitors and
−I
I
I
Lo
IN,AVG
C,MAX
I
P CIN + I CIN,RMS 2 @ ESR_per_capacitor N IN
C,MIN
0 A
is the peak−to−peak ripple current in the output
Figure 24. Input Capacitor Current for a
DI Lo + (V IN * V OUT ) @ D (Lo @ f SW )
FET On,
Caps Discharging
N IN + I CIN,RMS I RMS,RATED
) DI C,IN 2 3) ) I IN,AVG 2 @ (1 * 4D)] 1 2
Four−Phase Converter
CIN,RMS
t
ON
FET Off,
Caps Charging
I
C,IN
RMS,RATED
) based on the RMS ripple
= I
C,MAX
− I
):
T/4
C,MIN
IN
) to provide the
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NCP5314
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inrush currents reduce the expected life of the input
capacitors. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
the first few PWM cycles immediately after a step−load
change is applied as shown in Figure 25. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously, so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (I
capacitors (ESR
capacitors (N
current is shared equally between all phases, the output
voltage at full transient load will be:
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as:
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors ( V
capacitors (N
current in the output inductor according to:
inductor (V
to the input voltage V
drop across the input capacitors, V
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
dI
rate.
V OUT,FULL−LOAD +
DV Lo + V IN * V OUT,FULL−LOAD
IN
The worst case input current slew rate will occur during
When the control MOSFET (Q1 in Figure 25) turns ON,
The differential voltage across the output inductor will
Current changes slowly in the input inductor so the input
Before the load is applied, the voltage across the input
/dt
MAX
V OUT,NO−LOAD * (I O,MAX f) @ ESR OUT N OUT
+ V IN * V OUT,NO−LOAD
DV Ci + ESR IN N IN @ dI Lo dt @ t ON
O,MAX
) (I O,MAX f) @ ESR OUT N OUT
Li
is the maximum allowable input current slew
OUT
) is very small and the input capacitors charge
IN
+ ESR IN N IN @ dI Lo dt @ D f SW
Ci
Li MIN + V Li
), their per capacitor ESR (ESR
), the per capacitor ESR of the output
OUT
) as shown in Figure 25. Assuming the load
) is determined by the number of input
dI Lo dt + DV Lo Lo
IN
) and the number of the output
+ DV Ci
. After the load is applied, the voltage
dI IN dt MAX
dI IN dt MAX
Ci
, appears across the
IN
) and the
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