MCP3301-I/P Microchip Technology, MCP3301-I/P Datasheet - Page 21

• Manufacturer Part Number: MCP3301-I/P
• Description: 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface
• Manufacturer: Microchip Technology

7.3
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. Using a hardware SPI port
with the MCP3301 is very easy, because each conver-
sion requires 16 clocks. As an example, Figure 7-4 and
Figure 7-5 show how the MCP3301 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3301 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3301. Figure 7-4 depicts the operation shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the sign bit is clocked out of the ADC on the
falling edge of the third clock pulse, followed by the
remaining 12 data bits (MSB first). After the first eight
FIGURE 7-4:
FIGURE 7-5:
2001 Microchip Technology Inc.
D
D
CLK
CLK
Using the MCP3301 with
Microcontroller (MCU) SPI Ports
CS
CS
OUT
OUT
SPI Communication with the MCP3301 using 8-bit segments (Mode 0,0: SCLK idles low).
SPI Communication with the MCP3301 using 8-bit segments (Mode 1,1: SCLK idles high).
HI-Z
HI-Z
?
?
1
1
Data stored into MCU receive register
Data stored into MCU receive register
after transmission of first 8 bits
?
after transmission of first 8 bits
?
2
2
NULL
BIT SB B11 B10 B9
NULL
BIT SB
0
0
3
3
SB
SB
4
4
B11 B10 B9
B11 B10 B9
B11 B10 B9
5
5
6
6
7
7
B8
B8
B8
8
B8
8
B7
B7
B7
B7
Data stored into MCU receive register
9
Data stored into MCU receive register
9
after transmission of second 8 bits
after transmission of second 8 bits
B6
B6
B6
B6
10
10
B5
B5
B5
B5
11
11
B4
B4
B4
B4
clocks have been sent to the device, the microcontrol-
ler’s receive buffer will contain two unknown bits (the
output is at high impedance for the first two clocks), the
null bit, the sign bit and the highest order four bits of the
conversion. After the second eight clocks have been
sent to the device, the MCU receive register will contain
the lowest order 8 data bits. Notice on the falling edge
of clock 16 that the ADC has begun to shift out LSB first
data.
Figure 7-5 shows the same scenario in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the ADC outputs data on the falling
edge of the clock and the MCU latches data from the
ADC in on the rising edge of the clock.
12
12
B3
B3
B3
B3
13
13
B2
B2
B2
B2
14
14
B1
B1
B1
B1
15
15
B0
B0
B0
B0
16
16
B1
HI-Z
HI-Z
LSB first data begins
to come out
LSB first data begins
to come out
MCU latches data from ADC
on rising edges of SCLK
MCU latches data from ADC
on rising edges of SCLK
Data is clocked out of
ADC on falling edges
Data is clocked out of
ADC on falling edges
MCP3301
X = Don’t Care Bits
X = Don’t Care Bits
DS21700A-page 21