MCP3301-I/P Microchip Technology, MCP3301-I/P Datasheet - Page 15

• Manufacturer Part Number: MCP3301-I/P
• Description: 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface
• Manufacturer: Microchip Technology

6.0
6.1
The MCP3301 A/D converter employs a conventional
SAR architecture. With this architecture, the potential
between the IN+ and IN- inputs are simultaneously
sampled and stored with the internal sample circuits for
1.5 clock cycles(t
input hold switches of the converter open and the
device uses the collected charge to produce a serial
13-bit binary two’s complement output code. This con-
version process is driven by the external clock and
must include 13 clock cycles, one for each bit. During
this process, the most significant bit (MSB) is output
first. This bit is the sign bit and indicates if the IN+ or IN-
input is at a higher potential.
FIGURE 6-1:
FIGURE 6-2:
IN+
IN-
2001 Microchip Technology Inc.
Legend
VA
I
C
LEAKAGE
Hold
Hold
SAMPLE
CHx
APPLICATIONS INFORMATION
Conversion Description
C
R
R
VA
SS
V
R
PIN
SS
SS
T
S
=
=
=
=
=
=
=
=
=
Simplified Block Diagram.
Analog Input Model.
CHx
C
C
ACQ
SAMP
SAMP
signal source
source impedance
input channel pad
input pin capacitance
threshold voltage
leakage current at the pin
due to various junctions
sampling switch
sampling switch resistor
sample/hold capacitance
). Following this sample time, the
+
7 pF
-
C
Comp
PIN
CDAC
V
DD
D
13-Bit SAR
V
V
Register
OUT
T
T
Shift
= 0.6V
= 0.6V
I
±1 nA
LEAKAGE
6.2
The analog input of the MCP3301 is easily driven either
differentially or single ended. Any signal that is com-
mon to the two input channels will be rejected by the
common mode rejection of the device. During the
charging time of the sample capacitor, a small charging
current will be required. For low source impedances,
this input can be driven directly. For larger source
impedances, a larger acquisition time will be required
due to the RC time constant that includes the source
impedance. For the A/D Converter to meet specifica-
tion, the charge holding capacitor (C
given enough time to acquire a 13-bit accurate voltage
level during the 1.5 clock cycle acquisition period.
An analog input model is shown in Figure 6-2. This
model is accurate for an analog input, regardless if it is
configured as a single ended input or the IN+ and IN-
input in differential mode. In this diagram, it is shown
that the source impedance (R
sampling switch (R
time that is required to charge the capacitor (C
Consequently, a larger source impedance with no addi-
tional acquisition time increases the offset, gain, and
integral linearity errors of the conversion. To overcome
this a slower clock speed can be used to allow for the
longer charging time. Figure 6-3 shows the maximum
clock speed associated with source impedances.
Driving the Analog Input
SS
Sampling
Switch
SS
R
) impedance, directly affecting the
S
= 1 k
V
MCP3301
S
SS
C
= DAC capacitance
= 25 pF
) adds to the internal
SAMPLE
DS21700A-page 15
SAMPLE
) must be
SAMPLE
).