SC2596 Semtech Corporation, SC2596 Datasheet - Page 9

• Manufacturer Part Number: SC2596
• Description: Low Voltage Integrated DDR Termination Regulator
• Manufacturer: Semtech Corporation

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Thermal shutdown
The SC2596 has built-in thermal detected circuit to pre-
vent this device from over temperature and damage.
The SC2596 goes into shunt down mode when tem-
perature is higher than 165
will release when the temperature of device drop down
by 10
AVCC and PVCC
AVCC and PVCC are the input supply pins for the SC2596.
AVCC is supply voltage for all the internal control circuitry.
The AVCC voltage has to be greater than its UVLO thresh-
old voltage (2.1V typical) to allow the SC2596 to be nor-
mal operation.
The PVCC pin provides the rail voltage from where the
VTT pin draws load current. There is a limitation between
AVCC and PVCC. The PVCC voltage must be less or equal
to AVCC voltage to ensure the correct VTT output voltage
regulation.
VSENSE
VSENSE pin is a feedback pin from VTT plane. VTT plane
is always a narrow and long strip plane in most
montherboard applications. This long strip plane will
© 2007 Semtech Corp.
Overview
Double Data Rate (DDR) SDRAM was defined by JEDEC
1997. Its clock speed is the same as previous SDRAM
but data transfer speed is twice than previous SDRAM.
By now, the requirement voltage range is changed from
3.3V to 2.5V or 1.8V; the power dissipation is smaller
than SDRAM. For above reasons, it is very popular and
widely used in M/B, N/B, Video-cards, CD ROM drives,
Disk drives.
Regarding the DDR power management solution, there
are two topologies can be selected for system designers.
One is switching mode regulator that has bigger sink/
source current capability, but the cost is higher and needs
more board space. Another solution is linear mode regu-
lator, which costs less, and needs less board space. For
two DIMM motherboards, system designers usually
choose the linear mode regulator for DDR power man-
agement solution.
POWER MANAGEMENT
Application Information
O
C.
O
C. The protection condition
9
cause a large trace inductance and trace resistance.
Consider the load transient condition, a fast load cur-
rent going through VTT strip plane will create a voltage
spike on VTT plane and a DC voltage drop for load current.
It is recommanded the VSENSE pin should be connected
center of VTT plane to improve regulation and transient
response.
A longer trace of VSENSE may pick up noise and cause
the error of load regulation. Hence designer should avoid
a longer trace between VSENSE to VTT plane. A 100nF
ceramic capacitor close to VSENSE pin is required.
VREF
VREF pin is an output pin to provid internal reference
voltage. System designer can use the voltage for
Northbridge chipset and memory. It is necessary to add
a ceramic capacitor (100nF) from VREF pin to ground
with shortest trace.
Typical Application Circuits & Waveforms
Four different application circuits are shown below in Fig-
ure 1, Figure 2, Figure 3 and Figure 4. Each circuit is
designed for a specific condition. See Note a. and b.
below for recommended power up sequencing.
Application_1: Standard SSTL-2 Application
The AVCC pin, PVCC pin and the V
together for SSTL-2 application (Figure 1). It only needs
a 2.5V power rail for normal operation. System designer
can save the PCB space and reduce the cost.
2.5V
VDDQ
1.25V
EN
VREF
Figure 1: Standard SSTL-2 application.
0
10nF
1
2
3
4
100nF
Cref
GND
EN
VSENSE
VREF
SC2596
VDDQ
PVCC
AVCC
VTT
8
7
6
5
DDQ
pin can be tied
Cin1
1uF
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SC2596
100uF
Cin2
1.25V
220uF
Cout
VTT