KSC-3000 Kodak, KSC-3000 Datasheet - Page 22

• Manufacturer Part Number: KSC-3000
• Description: Color Processor Firmware Code Providing 24-bit RGB Color Image Data at 1 Megapixel Resolution And 30 Frames/second.
• Manufacturer: Kodak

IMAGE SENSOR SOLUTIONS
Image Information
The pixels per line and lines per frame value should be programmed to indicate the actual number of pixels the
KSC-3000 will be receiving*. Pixels per line are the number of elements within each line valid, and pixels per
frame are the number of elements within each frame valid.
The color filter array (CFA) start pixel and start line bits are intended to be set according to the staring point of the
Bayer pattern generated by the CFA. By default, it is assumed that the first pixel received will be a green pixel on a
row with green and red pixels.
* If the user wants to generate paxel data the pixels per line should not be set to less than 576 or there
will not be enough clocks cycles during the last three lines to append all of the paxel data to the image
data. 24X36 paxels = 864, times 4 data elements per paxel = 3456, divided by 2 paxel elements
produced per clock cycle = 1728, divided by 3 line times = 576.
Serial Communications
The serial interface is a three-wire bi-directional communication channel. It consists of a clock signal (SCK or
SerClock), a bi-directional data signal (SDATA or SerData), and a load signal (SL or SerLoad) that operates as a
chip select to enable communications on the channel. The serial interface provides access to KCS-3000 internal
registers and memory locations. Please refer to Table 8 – KSC-3000 Memory Map for a description of the
accessible registers/memories.
The serial interface supports read and write cycles as shown in Figure 6 and Figure 7. All data provided to the KCS-
3000 on SerData are qualified by the rising edge of SerClock and the assertion of SerLoad. The SerLoad signal is
used to frame a read/write cycle. In a read cycle, the data is driven onto SerData on the falling edge of the clock.
The number of SerClock pulses provided to read/write the data before SerLoad is deasserted must exactly match the
register/memory width that is being accessed.
The interface also supports burst mode transactions (not shown) such that the address is only specified for the first
location to be read/written and subsequent address values are calculated internally by the KCS-3000. This is
accomplished by extending the SerLoad signal at the end of a single read/write transaction and providing the correct
number of SerClock pulses to clock out/in the read/write data for the next sequential address location. The format of
a single read/write cycle is merely a burst mode cycle that provides enough data for only the first address location.
Note that burst mode transactions are not possible across non-contiguous addresses.
The serial interface also includes some error detection logic. These errors are latched into the serial interface status
register and will remain persistent until the serial interface status register is explicitly cleared via a write cycle.
Since certain error conditions may result in the serial interface being unable to provide read access to the status
register, some of these status bits are routed to LEDs on the reference design. Please refer to Table 2 - Diagonstic
Connections for these details.
K S C - 3 0 0 0 R e v 1 . 0
22
w w w . k o d a k . c o m / g o / i m a g e r s
5 8 5 - 7 2 2 - 4 3 8 5
E m a i l : i m a g e r s @ k o d a k . c o m