KSC-3000 Kodak, KSC-3000 Datasheet - Page 19

• Manufacturer Part Number: KSC-3000
• Description: Color Processor Firmware Code Providing 24-bit RGB Color Image Data at 1 Megapixel Resolution And 30 Frames/second.
• Manufacturer: Kodak

IMAGE SENSOR SOLUTIONS
This register contains only one control bit that is used to reset the signature generated by the signature analyzer to
“0x000001”. The control bit must be asserted and deasserted while the FrameValid input is inactive and the TIG is
not enabled in order to guarantee a clean reset.
Interpolation (Register 006)
Default: 32
The color interpolation stage uses a patented adaptive cubic spline interpolation algorithm. The algorithm computes
a smoothing spline and a sharpening spline, and uses them to adaptively preserve edges and suppress noise.
Increasing the value of the Edge parameter will increase the weighting of the sharpening spline over the smoothing
spline. A large value will cause aggressive edge enhancement. A small value will cause aggressive smoothing. The
default value of 32 produces an image with a good balance of sharpening and smoothing.
The interpolator uses a 4x4 kernel, which results in the output image having three fewer lines than the input image.
Output FIFO Control (Register 008)
Default: 0
This register specifies the minimum line blanking interval (LBI) between lines on the output of the device. The
following paragraph is a contextual description that explains the purpose of this register value.
The C1 design contains an output FIFO to collect pixels so that a line transfer does not begin on the output until a
full line is available. Therefore, the LBI on the output is generally constrained by the LBI on the input. However,
once a full image has been received at the input, the portion of the image that remains in the pipeline of the C1
FPGA must be flushed out in order to complete the image on the output. At this point, the LBI on the output is no
longer being constrained by the LBI on the input and, therefore, the output LBI is controlled by the output FIFO
control register. Since the pipeline stores two image lines in addition to the paxel data that is output in the last three
lines, there are a total of five lines* at the end of the image that will be output with the minimum LBI specified in
the output FIFO control register.
This minimum LBI value should be set the same as or lower than LBI on the input of the device during normal
operation, or the LBI specified in the TIG control register when the TIG is enabled. Otherwise, an overflow and/or
underflow condition may occur in the output FIFO.
* It is assumed that the FrameValid and LineValid inputs will deassert simultaneously at the end of each
frame. If this is not the case, the delay between the deassertion of LineValid and FrameValid will be
added to the LBI preceding the fifth last line on the output. This is due to the fact that the end of frame
must be fully qualified by the deassertion of both LineValid and FrameValid before flushing of the internal
pipeline can begin.
Dark Offset Correction (Register 009)
Default: 0
Setting the dark offset register to values other than 0 will cause the value each pixel in the image to be reduced by
the value of the register setting, up to a maximum of 255.
K S C - 3 0 0 0 R e v 1 . 0
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