KSC-1000 Kodak, KSC-1000 Datasheet - Page 34

• Manufacturer Part Number: KSC-1000
• Description: Timing Generator Full Program-ability Through a Simple 3-wire Serial Interface Allows Maximum Flexibility in Sensor Operation.
• Manufacturer: Kodak

IMAGE SENSOR SOLUTIONS
34
Frame Table Sequence Control
Frame tables can be coded such that no external
intervention is required for sequencing within a
frame table or sequencing between frame tables.
However, there may be instances where external
intervention is desired.
system, an external controller may be monitoring
the state of the shutter button. Detecting a button
press would start a camera system integrate and
readout operation.
An external controller can use the VD signal to
control frame table sequencing.
example the frame table could be coded in such
K S C - 1 0 0 0 R e v 1 . 0
17:29
30:32
10
11
12
13
14
15
16
33
9
w w w . k o d a k . c o m / g o / i m a g e r s
AFE Clock Enable 0 = De-assert ADCLK, DATACLK, SHP_1, SHP_2, SHD_1, SHD_2
CLPDM2 Enable
CLPDM1 Enable
CLPOB2 Enable
CLPOB1 Enable
Pblk_Idle_Val
PBLK Enable
Address 2:0
Address 3
Enable
Count
Flag
In a typical camera
Table 22 Frame Table Data Descriptor
0 = De-assert CLPOB
1 = Allow CLPOB to run as specified in General Setup Register
0 = De-assert CLPOB
1 = Allow CLPOB to run as specified in General Setup Register
0 = De-assert PBLK
1 = Allow PBLK to run as specified in General Setup Register
Level held during de-asserted state
Refer to Frame Table Event Descriptor for details
Refer to Frame Table Event Descriptor for details
Refer to Frame Table Event Descriptor for details
Refer to Frame Table Event Descriptor for details
1 = Assert AMP_ENABLE; directly controls the output pin
1 = Allow clocks to run
0 = De-assert CLPDM
1 = Allow CLPDM to run as specified in General Setup Register
0 = De-assert CLPDM
1 = Allow CLPDM to run as specified in General Setup Register
In the above
5 8 5 - 7 2 2 - 4 3 8 5
a way that the camera system is performing a
decimated preview image readout indefinitely
until the VD signal is asserted. Upon detecting
the VD signal assertion, execution of the current
line table sequence is completed and the frame
table execution continues at the instruction
destination address.
VD is asserted by driving to a logic high. The
state of the VD line is ignored for those frame
table instructions listed in Table 23 that have the
state of VD event listed as don’t care (X). Frame
table instructions are described in Table 23.
E m a i l : i m a g e r s @ k o d a k . c o m