KSC-1000 Kodak, KSC-1000 Datasheet - Page 30

• Manufacturer Part Number: KSC-1000
• Description: Timing Generator Full Program-ability Through a Simple 3-wire Serial Interface Allows Maximum Flexibility in Sensor Operation.
• Manufacturer: Kodak

IMAGE SENSOR SOLUTIONS
30
Data Length
Signal Polarity Register
Each of the outputs associated with this table have
an XOR in their logic path to control the polarity of
the output signal. A ‘0’ in the following register
means that the output will be ‘0’ when it is inactive.
A ‘1’ in the following register inverts the polarity
defined in the line table for the V1_1, V1_2, V2_1,
V2_2,V_DISCGH, and FAST_DUMP signals, and
K S C - 1 0 0 0 R e v 1 . 0
Register 5
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
w w w . k o d a k . c o m / g o / i m a g e r s
H1_1_IDLE_VAL ( level held during vertical clocking)
H1_2_IDLE_VAL ( level held during vertical clocking)
H2_1_IDLE_VAL ( level held during vertical clocking)
H2_2_IDLE_VAL ( level held during vertical clocking)
HLG_1_IDLE_VAL ( level held during vertical clocking)
HLG_2_IDLE_VAL ( level held during vertical clocking)
RG_IDLE_VAL (level held during de-asserted state)
SHP_1_IDLE_VAL (level held during de-asserted state)
SHP_2_IDLE_VAL (level held during de-asserted state)
SHD_1_IDLE_VAL (level held during de-asserted state)
SHD_2_IDLE_VAL (level held during de-asserted state)
ADCLK_IDLE_VAL (level held when signal is disabled)
DATA_CLK_IDLE_VAL (level held when signal is disabled)
CLPOB_IDLE_VAL (level held during de-asserted state)
CLPDM_IDLE_VAL (level held during de-asserted state)
AMP_ENABLE_IDLE_VAL (level held during de-asserted state)
FRAME_VALID_IDLE_VAL (level held during de-asserted state)
LINE_VALID_IDLE_VAL (level held during de-asserted state)
INTEGRATE_START_IDLE_VAL (level held during de-asserted state)
V1_1_IDLE_VAL (used in conjunction with V1_2 to define non-clocking state of KSC-
2000 clock driver ASIC)
V1_2_IDLE_VAL (used in conjunction with V1_1 to define non-clocking state of KSC-
2000 clock driver ASIC)
V2_1_IDLE_VAL (used in conjunction with V2_2 to define non-clocking state of KSC-
2000 clock driver ASIC)
V2_2_IDLE_VAL (used in conjunction with V2_1 to define non-clocking state of KSC-
2000 clock driver ASIC)
V_DISCHG_IDLE_VAL (level held during de-asserted state)
FAST_DUMP_IDLE_VAL (level held during de-asserted state)
Table 17 Signal Polarity Register Map
Signal Polarity Register
5 8 5 - 7 2 2 - 4 3 8 5
Register Field
means that the output will be ‘1’ when it is inactive
for the other signals. For example, an H clock’s
idle value is the level it is held at during vertical
clocking. For PBLK, CLPOB, and CLDPM, the idle
value is the level it is held at during horizontal
clocking in readout mode.
E m a i l : i m a g e r s @ k o d a k . c o m
(Decimal)
Default
0
0
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
0