PIC16F505 Microchip Technology, PIC16F505 Datasheet - Page 41

• Manufacturer Part Number: PIC16F505
• Description: (PIC1xF50x) 8-Bit Flash Microcontrollers
• Manufacturer: Microchip Technology

7.0
What sets a microcontroller apart from other proces-
sors are special circuits that deal with the needs of real-
time
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power-
saving operating modes and offer code protection.
These features are:
• Oscillator Selection
• Reset:
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
• Clock Out
REGISTER 7-1:
 2004 Microchip Technology Inc.
bit 11
bit 11-5
bit 4
bit 3
bit 2
bit 1-0
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from Sleep on Pin Change
—
applications.
SPECIAL FEATURES OF THE
CPU
Unimplemented: Read as ‘0’
MCLRE: GP3/MCLR Pin Function Select bit
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to V
CP: Code Protection bit
1 = Code protection off
0 = Code protection on
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC<1:0>: Oscillator Selection bits
11 = EXTRC = external selection bits
10 = INTRC = internal RC oscillator
01 = XT oscillator
00 = LP oscillator
Legend:
R = Readable bit
-n = Value at POR
Note 1: Refer to the “PIC12F508/509 Memory Programming Specifications” (DS41227) to determine how to access
—
the Configuration Word. The Configuration Word is not user addressable during device operation.
CONFIGURATION WORD FOR PIC12F508/509
The
—
PIC12F508/509/16F505
—
W = Writable bit
‘1’ = bit is set
—
Preliminary
—
PIC12F508/509/16F505
—
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared
The PIC12F508/509/16F505 devices have a Watchdog
Timer, which can be shut off only through configuration
bit WDTE. It runs off of its own RC oscillator for added
reliability. If using HS (PIC16F505), XT or LP selectable
oscillator options, there is always an 18 ms (nominal)
delay provided by the Device Reset Timer (DRT),
intended to keep the chip in Reset until the crystal
oscillator is stable. If using INTRC or EXTRC, there is
an 18 ms delay only on V
on-chip, most applications need no external Reset
circuitry.
The Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through a change on input pins or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application,
including an internal 4 MHz oscillator. The EXTRC
oscillator option saves system cost while the LP crystal
option saves power. A set of configuration bits are used
to select various options.
7.1
The
consist of 12 bits. Configuration bits can be
programmed to select various device configurations.
Three bits are for the selection of the oscillator type;
(two bits on the PIC12F508/509), one bit is the
Watchdog Timer enable bit, one bit is the MCLR enable
bit and one bit is for code protection (Register 7-1,
Register 7-2).
DD
MCLRE
PIC12F508/509/16F505
Configuration Bits
(1)
CP
WDTE
DD
x = bit is unknown
power-up. With this timer
Configuration
FOSC1
DS41236A-page 39
FOSC0
bit 0
Words