AT91SAM7X512 ATMEL Corporation, AT91SAM7X512 Datasheet - Page 29

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AT91SAM7X512

Manufacturer Part Number
AT91SAM7X512
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet

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9.5
9.6
9.7
6120DS–ATARM–03-Oct-06
Debug Unit
Periodic Interval Timer
Watchdog Timer
• Vectoring
• Protect Mode
• Fast Forcing
• General Interrupt Mask
• Comprises:
• Two-pin UART
• Debug Communication Channel Support
• Chip ID Registers
• 20-bit programmable counter plus 12-bit interval counter
• 12-bit key-protected Programmable Counter running on prescaled SLCK
• Provides reset or interrupt signals to the system
• Counter may be stopped while the processor is in debug state or in idle mode
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes interrupt service routine branch and execution
– One 32-bit vector register per interrupt source
– Interrupt vector register reads the corresponding current interrupt vector
– Easy debugging by preventing automatic operations
– Permits redirecting any interrupt source on the fast interrupt
– Provides processor synchronization on events without triggering an interrupt
– One two-pin UART
– One Interface for the Debug Communication Channel (DCC) support
– One set of Chip ID Registers
– One Interface providing ICE Access Prevention
– USART-compatible User Interface
– Programmable Baud Rate Generator
– Parity, Framing and Overrun Error
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
– Identification of the device revision, sizes of the embedded memories, set of
– Chip ID is 0x275C 0A40 (VERSION 0) for AT91SAM7X512
– Chip ID is 0x275B 0940 (VERSION 0) for AT91SAM7X256
– Chip ID is 0x275A 0740 (VERSION 0) for AT91SAM7X128
AT91SAM7X512/256/128 Preliminary Summary
peripherals
29

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