AD8304 Analog Devices, AD8304 Datasheet - Page 15

• Manufacturer Part Number: AD8304
• Description: 160 DB Logarithmic Amplifier With Photo-diode Interface
• Manufacturer: Analog Devices

The minimum voltage that can be accurately measured is then
limited only by the drift in the input offset of the AD8304. The
specifications show the maximum spread over the full tempera-
ture and supply range. Over a limited temperature range, and with
a regulated supply, the offset drift will be lower; in this situa-
tion, processing of inputs down to 5 mV is practicable.
The input system of the AD8304 is quasi-differential, so VSUM
can be placed at an arbitrary reference level V
range, and used as the “signal LO” of the source. For example,
using V
± 2.5 V range.
Providing Negative Outputs and Rescaling
As noted, the AD8304 allows the buffer to drive a load to nega-
tive voltages with respect to ACOM, the analog common pin,
which is grounded. A negative supply capable of supporting the
input current I
flows out of the VNEG pin, and the load current at VLOG. For
the example shown in Figure 14 this totals to less than 20 mA,
when driving a 1 kΩ load as far as –4 V.
The use of a much larger value for the intercept may be useful in
certain situations. In this example, it has been moved up four
decades, from the default value of 100 pA to the center of the full
eight decades range at 1 mA. Using a voltage input as described
above, this corresponds to an altered voltage-mode intercept, V
which would be 1 V for R
the larger output swing, the gain of the buffer has been increased
to 4.5 , resulting in a scaling of 900 mV/decade and a full-scale
output of ± 3.6 V.
Inverting the Slope
The buffer is essentially an uncommitted op amp that can be
used to support the operation of the AD8304 in a variety of
ways. It can be completely disconnected from the signal chain
when not needed. Figure 15 shows its use as an inverting ampli-
fier; this changes the polarity of the slope. The output can either
be repositioned to all positive values by applying a fraction of
V
supply. The full design for a practical application is left unde-
fined in this brief illustration, but a few cases will be discussed.
V
REF
P
RIN
V
SIG
1k
NC = NO CONNECT
to the BFIN pin, or range negative when using a negative
I
PD
10k
NC
P
= 5 V and V
V
4
6
3
5
LOW
VPDB
VSUM
VSUM
INPT
PD
VPS2
must be used, the fraction of quiescent bias that
1
PDB
VNEG
10
N
V
= –3 V, V
N
IN
PWDN
~10k
= 1 MΩ. To take full advantage of
COMPENSATION
ACOM
TEMPERATURE
BIAS
2
LOW
14
can be any voltage within a
VPS1
0.5V
VREF
VOUT
12
5k
LOW
11
BFNG
, over a wide
BFIN
13
7
8
9
V
P
VLOG
VREF
RB
22.6k
V
OUT
RC
12.4k
RA
13.3k
RL
1k
Z
,
For example, suppose we need a slope of –30 mV/dB; this
requires the gain to be three. Since V
tance of 5 kΩ, R
supply is available, the output voltage can swing below ground,
and the BFIN pin may be grounded. But a negative slope is still
possible when only a single supply is used; a positive offset, V
is applied to this pin, as indicated in Figure 15. In general, the
resulting output voltage can be expressed as:
When the gain is set to 1 (R
directly to BFIN, in which case the starting point for the output
response is at 4 V. However, since the slope in this case is only
–0.2 V/decade, the full current range will only take the output
down by 1.6 V. Clearly, a higher slope (or gain) is desirable, in
which case V
railing the output at low currents. If V
VOUT now starts at 4.8 V and falls through this same voltage
toward ground with a slope of –0.6 V per decade, spanning the
full range of I
Programmable Level Comparator with Hysteresis
The buffer amplifier and reference voltage permit a calibrated
level detector to be realized. Figure 16 shows the use of a 10-bit
MDAC to control the setpoint to within 0.1 dB of an exact
value over the 100 dB range of 1 nA ≤ I
full-scale output of the MDAC is equal to that of its reference.
The 2 V V
corresponding to an input of 1 nA. Since 100 dB at the VLOG
interface corresponds to a 1 V span, the resistor network is
calculated to provide a maximum V
the required 10% of V
In this example, the hysteresis range is arranged to be 0.1 dB,
(1 mV at VLOG) when using a 5 V supply. This will usually be
adequate to prevent noise that causes the comparator output to
thrash. That risk can be reduced further by using a low-pass
filtering capacitor at V
bandwidth.
NC = NO CONNECT
R1
750
C1
1nF
10nF
I
PD
V
NC
OUT
6
3
4
5
REF
=
VPDB
VSUM
VSUM
INPT
V
–
N
OFS
PD



(–0.5V TO –3V)
also sets the minimum value of V
VPS2
5
.
B
R
should be set to a smaller voltage to avoid
k
must be 15 kΩ. In cases where a small negative
1
B
Ω
PDB
VNEG
10



V
REF
LOG
Y
PWDN
~10k
.
×
(shown dotted) to decrease the noise
log
ACOM
COMPENSATION
BIAS
TEMPERATURE
B
2
10
= 5 kΩ) the 2 V V



14
I
I
PD
Z
SPT
LOG

 +

OFS
0.5V
VPS1
of 1.2 V while adding
PD
exhibits a source resis-
V
VREF
= 1.2 V and G = 3 ,
VOUT
OFS
≤ 100 µA when the
12
5k
11
SPT
AD8304
BFNG
BFIN
REF
to 0.2 V,
13
7
8
9
V
can be tied
P
VLOG
VREF
V
OFS
(16)
RB
OFS
V
OUT
,