AD8304 Analog Devices, AD8304 Datasheet - Page 13

• Manufacturer Part Number: AD8304
• Description: 160 DB Logarithmic Amplifier With Photo-diode Interface
• Manufacturer: Analog Devices

The use of a capacitor at the VLOG pin to create a single-pole
filter has already been mentioned. The small added cost of the
few external components needed to realize a multipole filter is
often justified in a high-performance measurement system. Fig-
ure 8 shows a Sallen-Key filter structure. Here, the resistor
needed at the front of the network is provided entirely by the
accurate 5 kΩ present at the VLOG output; R
value. The corner frequency and Q (damping factor) are deter-
mined by the capacitors C
R
using various gains is provided in Table IV; the values shown are
for a 1 kHz corner, (see also TPC 12). This frequency can be
increased or decreased by scaling the capacitor values. Note that
R
suggested values to maintain the shape of the ac amplitude response
and pulse overshoot provided by the values shown in this table.
In all cases, the roll-off rate above the corner is 40 dB/dec.
R
(k )
0
10
12
24
NOTES
The corner frequency can be adjusted by scaling capacitors C
example, to reduce the corner frequency to 100 Hz, raise the values of C
C
Operation in Comparator Modes
In certain applications, the need may arise to generate a logical
output when the input current has reached a certain value. This
can be easily addressed by using a fraction of the voltage refer-
ence to provide the set-point (threshold) and using the buffer
without feedback in a comparator mode, as illustrated in Fig-
ure 9. Since V
2 V reference is more than adequate to cover the full dynamic
range of I
unchanged, while the release point for decreasing currents is
5 dB below this. Raising R
0.5 dB, or it may be increased using a lower value for R
NC = NO CONNECT
See TPC 12.
B
B
D
A
R1
750k
C1
1nF
Table IV. Two-Pole Filter Parameters for 1 kHz Cutoff
Frequency
. A suggested starting point for choosing these components
10nF
, G, and the capacitor ratio C
by 10 .
I
PD
NC
R
(k )
open
10
8
6
6
3
4
5
PD
B
VSUM
VSUM
VPDB
INPT
VNEG
. Note that the threshold for an increasing I
VPS2
LOG
1
G
1
2
2.5
5
PDB
10
runs from ground up to 1.6 V maximum, the
PWDN
~10k
V
(V/decade)
0.2
0.4
0.5
1.0
Y
A
COMPENSATION
ACOM
H
TEMPERATURE
BIAS
and C
2
to 5 MΩ reduces the hysteresis to
14
A
/C
B
and the gain G = (R
B
0.5V
VPS1
should not deviate from the
VREF
R
(k )
11.3
6.02
12.1
10.0
VOUT
12
5k
D
11
B
BFNG
BFIN
will have a similar
A
13
C
(nF)
12
33
33
33
7
8
9
V
and C
P
VLOG
VREF
A
CA
RD
A
B
PD
H
RA
RB
. For
+ R
.
A
C
(nF)
12
22
18
18
is
and
B
B
)/
CB
V
OUT
Using a Negative Supply
Most applications of the AD8304 will require only a single supply
of 3.0 V to 5.5 V. However, to provide further versatility, dual
supplies may be employed, as illustrated in Figure 10.
The use of a negative supply, V
be placed exactly at ground level, because the input transistor
(Q1 in Figure 1) will have a negative bias on its emitter. V
be as small as –0.5 V, making the V
case. This bias need not be accurate, and a poorly defined source
can be used.
A larger supply of up to –5 V may be used. The effect on scaling
is minor. It merely moves the intercept by ~0.01 dB/V. Accord-
ingly, an uncertainty of 0.2 V in V
error of 0.002 dB. The slope is unaffected by V
earity will be degraded at the extremes of the dynamic range as
indicated in Figure 11. The bias current, buffer output (and its
load) current, and the full I
negative supply, and its supply capacity must be ensured for the
maximum current condition.
With the summing node at ground, the AD8304 may now be
used as a voltage-input log amp, simply by inserting a suitably
scaled resistor from the voltage source to the INPT pin. The
logarithmic accuracy for small voltages is limited by the offset of
the J-FET op amp, appearing between this pin and VSUM.
The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
mid-range value of I
NC = NO CONNECT
NC = NO CONNECT
R1
750
R1
750
C1
1nF
C1
1nF
10nF
I
I
PD
PD
NC
NC
4
4
6
3
5
6
3
5
VSUM
VSUM
VSUM
VSUM
VPDB
VPDB
INPT
INPT
V
VNEG
N
(–0.5V TO –3V)
VPS2
VPS2
1
1
PDB
PDB
PD
VNEG
10
10
. However, the voltage V
PWDN
PWDN
~10k
~10k
PD
COMPENSATION
COMPENSATION
ACOM
ACOM
TEMPERATURE
TEMPERATURE
BIAS
BIAS
all have to be absorbed by this
2
2
N
, allows the summing node to
14
14
N
CE
would result in a negligible
the same as for the default
VPS1
0.5V
0.5V
VPS1
VREF
VREF
VOUT
VOUT
12
12
5k
5k
11
11
N
LOG
AD8304
BFNG
BFNG
BFIN
BFIN
. The log lin-
remains
13
13
7
8
9
7
8
9
V
V
P
P
VLOG
VLOG
VREF
VREF
RH
RB
V
V
N
OUT
OUT
RG
RA
RA
may